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Weng-Fai Wong: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh
    A Performance and Power Co-optimization Approach for Modern Processors. [Citation Graph (0, 0)][DBLP]
    CIT, 2005, pp:822-828 [Conf]
  2. Qin Zhao, Joon Edward Sim, Weng-Fai Wong, Larry Rudolph
    DEP: detailed execution profile. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:154-163 [Conf]
  3. Weng-Fai Wong
    Targeted Data Prefetching. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2005, pp:775-786 [Conf]
  4. Rongrong Zhong, Yongxin Zhu, Weiwei Chen, Mingliang Lin, Weng-Fai Wong
    An Inter-Core Communication Enabled Multi-Core Simulator Based on SimpleScalar. [Citation Graph (0, 0)][DBLP]
    AINA Workshops (1), 2007, pp:758-763 [Conf]
  5. Zhenxin Sun, Weng-Fai Wong, Yongxin Zhu, Santhosh Kumar Pilakkat
    Design of clocked circuits using UML. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:901-904 [Conf]
  6. Yongxin Zhu, Weng-Fai Wong, Stefan Andrei
    An integrated performance and power model for superscalar processor designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:948-951 [Conf]
  7. Rodric M. Rabbah, Hariharan Sandanagobalane, Mongkol Ekpanyapong, Weng-Fai Wong
    Compiler orchestrated prefetching via speculation and predication. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:189-198 [Conf]
  8. Lakshmi N. Chakrapani, Pinar Korkmaz, Vincent John Mooney III, Krishna V. Palem, Kiran Puttaswamy, Weng-Fai Wong
    The emerging power crisis in embedded processors: what can a poor compiler do? [Citation Graph (0, 0)][DBLP]
    CASES, 2001, pp:176-180 [Conf]
  9. Liang Peng, Weng-Fai Wong, Chung-Kwong Yuen
    The Performance Model of SilkRoad - A Multithreaded DSM System for Clusters. [Citation Graph (0, 0)][DBLP]
    CCGRID, 2003, pp:495-501 [Conf]
  10. Qin Zhao, Rodric M. Rabbah, Saman P. Amarasinghe, Larry Rudolph, Weng-Fai Wong
    Ubiquitous Memory Introspection. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:299-311 [Conf]
  11. Vlad-Mihai Panait, Amit Sasturkar, Weng-Fai Wong
    Static Identification of Delinquent Loads. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:303-314 [Conf]
  12. C. M. Tan, C. P. Tan, Weng-Fai Wong
    Shell over a Cluster (SHOC): Towards Achieving Single System Image via the Shell. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2002, pp:28-0 [Conf]
  13. Liang Peng, Weng-Fai Wong, Chung-Kwong Yuen
    SilkRoad II: A Multi-Paradigm Runtime System for Cluster Computing. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2002, pp:443-444 [Conf]
  14. Alexander Maxiaguine, Yongxin Zhu, Samarjit Chakraborty, Weng-Fai Wong
    Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:128-133 [Conf]
  15. Krishna V. Palem, Surendranath Talla, Weng-Fai Wong
    Compiler Optimizations for Adaptive EPIC Processors. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2001, pp:257-273 [Conf]
  16. Yongxin Zhu, Weng-Fai Wong, Stefan Andrei
    Co-optimization of Performance and Power in a Superscalar Processor Design. [Citation Graph (0, 0)][DBLP]
    EUC Workshops, 2006, pp:868-878 [Conf]
  17. Zhiguo Ge, Hock-Beng Lim, Weng-Fai Wong
    A Reconfigurable Instruction Memory Hierarchy for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:7-12 [Conf]
  18. Jirong Liao, Weng-Fai Wong, Tulika Mitra
    A Model for Hardware Realization of Kernel Loops. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:334-344 [Conf]
  19. W. F. Wong, Eiichi Goto
    Fast Evaluation of the Elementary Functions in Double Precision. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:349-359 [Conf]
  20. Khaing Khaing Kyi Win, Weng-Fai Wong
    Cooperative Instruction Scheduling with Linear Scan Register Allocation. [Citation Graph (0, 0)][DBLP]
    HiPC, 2005, pp:528-537 [Conf]
  21. Lei He, Tulika Mitra, Weng-Fai Wong
    Configuration bitstream compression for dynamically reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:766-773 [Conf]
  22. Jinwoo Kim, Krishna V. Palem, Weng-Fai Wong
    A Framework for Data Prefetching Using Off-Line Training of Markovian Predictors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:340-347 [Conf]
  23. Ming-Dong Feng, Weng-Fai Wong, Chung-Kwong Yuen
    Design and Implementation of Abstract Machine for Parallel Lisp Compilation. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1995, pp:37-44 [Conf]
  24. C. P. Tan, Weng-Fai Wong, Chung-Kwong Yuen
    tmPVM - Task Migratable PVM. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:196-202 [Conf]
  25. Hock-Beng Lim, Yong Meng Teo, Protik Mukherjee, Vinh The Lam, Weng-Fai Wong, Simon See
    Sensor Grid: Integration ofWireless Sensor Networks and the Grid. [Citation Graph (0, 0)][DBLP]
    LCN, 2005, pp:91-99 [Conf]
  26. Ming-Dong Feng, Weng-Fai Wong, Chung-Kwong Yuen
    Compiling Parallel Lisp for a Shared Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Systems, 1995, pp:487-490 [Conf]
  27. Jinwoo Kim, Rodric M. Rabbah, Krishna V. Palem, Weng-Fai Wong
    Adaptive Compiler Directed Prefetching for EPIC Processors. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2004, pp:495-501 [Conf]
  28. Yongxin Zhu, Zhenxin Sun, Alexander Maxiaguine, Weng-Fai Wong
    Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream Processing. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2005, pp:154-159 [Conf]
  29. Kathy Dang Nguyen, Zhenxin Sun, P. S. Thiagarajan, Weng-Fai Wong
    Model-Driven SoC Design via Executable UML to SystemC. [Citation Graph (0, 0)][DBLP]
    RTSS, 2004, pp:459-468 [Conf]
  30. Chi-Hung Chi, Xiao-Yan Yu, Wenjie Zhang, Chen Ding, Weng-Fai Wong
    Data Integrity Framework and Language Support for Active Web Intermediaries. [Citation Graph (0, 0)][DBLP]
    WCW, 2004, pp:94-105 [Conf]
  31. Ming-Dong Feng, Weng-Fai Wong, Chung-Kwong Yuen
    BaLinda Lisp: Design and Implementation. [Citation Graph (0, 0)][DBLP]
    Comput. Lang., 1996, v:22, n:4, pp:205-214 [Journal]
  32. Liang Peng, Weng-Fai Wong, Chung-Kwong Yuen
    SilkRoad II: mixed paradigm cluster computing with RC_dag consistency. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2003, v:29, n:8, pp:1091-1115 [Journal]
  33. P. Spee, Weng-Fai Wong, M. Sato, E. Goto
    Evaluation of the continuation bit in the Cyclic Pipeline Computer. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1992, v:18, n:12, pp:1349-1361 [Journal]
  34. Weng-Fai Wong, Chung-Kwong Yuen
    A Model of Speculative Parallelism. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1992, v:2, n:, pp:265-272 [Journal]
  35. Chung-Kwong Yuen, Weng-Fai Wong
    A self interpreter for BaLinda Lisp. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Notices, 1990, v:25, n:7, pp:39-58 [Journal]
  36. Weng-Fai Wong, E. Goto
    Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:3, pp:278-294 [Journal]
  37. Weng-Fai Wong, E. Goto
    Fast Evaluation of the Elementary Functions in Single Precision. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:453-457 [Journal]
  38. Zhiguo Ge, Weng-Fai Wong, Hock-Beng Lim
    DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1343-1348 [Conf]
  39. Gordon J. Brebner, Samarjit Chakraborty, Weng-Fai Wong
    Editorial for the Special Issue on Field Programmable Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2007, v:47, n:1, pp:1-2 [Journal]

  40. A UML-based approach for heterogeneous IP integration. [Citation Graph (, )][DBLP]


  41. How to Do a Million Watchpoints: Efficient Debugging Using Dynamic Instrumentation. [Citation Graph (, )][DBLP]


  42. Pipa: pipelined profiling and analysis on multi-core systems. [Citation Graph (, )][DBLP]


  43. SilkRoad: A Multithreaded Runtime System with Software Distributed Shared Memory for SMP Clusters. [Citation Graph (, )][DBLP]


  44. A DVS-based pipelined reconfigurable instruction memory. [Citation Graph (, )][DBLP]


  45. A computing origami: folding streams in FPGAs. [Citation Graph (, )][DBLP]


  46. Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators. [Citation Graph (, )][DBLP]


  47. VOSCH: Voltage scaled cache hierarchies. [Citation Graph (, )][DBLP]


  48. A UML-Based Design Framework for Time-Triggered Applications. [Citation Graph (, )][DBLP]


  49. Automatically patching errors in deployed software. [Citation Graph (, )][DBLP]


  50. BSN Simulator: Optimizing Application Using System Level Simulation. [Citation Graph (, )][DBLP]


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