The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Tianzhou Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tianzhou Chen, Wei Hu, Bin Xie, Like Yan
    Real-Time Scheduling Algorithm Based on Set Division of Resource for Embedded Operating System. [Citation Graph (0, 0)][DBLP]
    CIT, 2006, pp:168- [Conf]
  2. Tianzhou Chen, Wei Hu, Yi Lian
    Power-Efficient Microkernel of Embedded Operating System on Chip. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:473-479 [Conf]
  3. Tianzhou Chen, Yi Lian, Wei Hu
    Chip OS: new architecture for next generation embedded system. [Citation Graph (0, 0)][DBLP]
    ESA, 2006, pp:118-120 [Conf]
  4. Tianzhou Chen, Jinhui Yu, Qunsheng Peng
    Style Conversion of Cartoon Animation. [Citation Graph (0, 0)][DBLP]
    Edutainment, 2006, pp:1074-1079 [Conf]
  5. Tianzhou Chen, Quan Gan, Wei Hu, Jiangwei Huang
    Communication Protocol Decomposition and Component-based Protocol Submodule. [Citation Graph (0, 0)][DBLP]
    IASTED Conf. on Software Engineering, 2005, pp:226-230 [Conf]
  6. Youtian Qu, Tianzhou Chen, Xu Hong
    An Agent Component-Oriented Software Process. [Citation Graph (0, 0)][DBLP]
    IAT, 2005, pp:459-462 [Conf]
  7. Tianzhou Chen, Yi Lian, Jiangwei Huang
    A New Approach for Predictable Hard Real-Time Transaction Processing in Embedded Database. [Citation Graph (0, 0)][DBLP]
    ICESS, 2004, pp:222-228 [Conf]
  8. Jiangwei Huang, Tianzhou Chen, Minjiao Ye, Yi Lian
    The Modeling for Dynamic Power Management of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICESS, 2004, pp:462-467 [Conf]
  9. Tianzhou Chen, Yi Lian
    New power aware multicast algorithm in mobile Ad hoc network. [Citation Graph (0, 0)][DBLP]
    ICWN, 2006, pp:269-274 [Conf]
  10. Huang Jiangwei, Chen Tianzhou, Qianjie Liangxiao
    Partitioning the program into different regions using dynamic and static approach with kernel-assisted in power management for embedded system. [Citation Graph (0, 0)][DBLP]
    IRI, 2006, pp:341-344 [Conf]
  11. Tianzhou Chen, Zhenjie He, Wei Hu
    Effectively implement AES for EFI/Tiano based on IA-32 Platform. [Citation Graph (0, 0)][DBLP]
    ITNG, 2006, pp:570- [Conf]
  12. Tianzhou Chen, Minjiao Ye
    Unified Mobile Protocol Stack with Network Sub-Protocol Component Framework. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2005, pp:64-69 [Conf]
  13. Tianzhou Chen, Yin Yan, Hongjun Dai, Hu Wei
    An Agile BSP Modeling Methodology: Cross Platform BSP Framework (CPBF). [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:126-132 [Conf]
  14. Tianzhou Chen, Hu Wei, Bin Xie, Like Yan
    A Real-Time Scheduling Algorithm for Embedded Systems With Various Resource Requirements. [Citation Graph (0, 0)][DBLP]
    IWNAS, 2006, pp:43-46 [Conf]
  15. Tianzhou Chen, Hu Wei, Wang Xiangsheng
    Smart File System: Embedded File System Based on NAND-Flash. [Citation Graph (0, 0)][DBLP]
    IWNAS, 2006, pp:65-66 [Conf]
  16. Tianzhou Chen, Hu Wei, Lian Yi
    Microkernel of Embedded Operating System in SRAM. [Citation Graph (0, 0)][DBLP]
    IWNAS, 2006, pp:57-58 [Conf]
  17. Tianzhou Chen, Zhao Yi, Hu Wei
    Assigning Program To Cache-Aware Scratchpad Concerning The Influence Of The Whole Embedded System. [Citation Graph (0, 0)][DBLP]
    IWNAS, 2006, pp:133-137 [Conf]
  18. Tianzhou Chen, Guobing Chen, Hongjun Dai, Qinsong Shi
    A function-based on-chip communication design in the heterogeneous multi-core architecture. [Citation Graph (0, 0)][DBLP]
    MUE, 2007, pp:1086-1092 [Conf]
  19. Tianzhou Chen
    A Novel Architecture for Embedded Database Management System on Chip. [Citation Graph (0, 0)][DBLP]
    MUE, 2007, pp:253-259 [Conf]
  20. Wenli Cai, Tianzhou Chen, Jiaoying Shi
    Rendering of Surface and Volume Details in Volume Data. [Citation Graph (0, 0)][DBLP]
    Comput. Graph. Forum, 1995, v:14, n:3, pp:421-430 [Journal]
  21. Lingxiang Xiang, Jiangwei Huang, Weihua Sheng, Tianzhou Chen
    The Design and Implementation of the DVS Based Dynamic Compiler for Power Reduction. [Citation Graph (0, 0)][DBLP]
    APPT, 2007, pp:233-240 [Conf]
  22. Tianzhou Chen, Feng Sha, Wei Hu, Qingsong Shi
    A New Type of Embedded File System Based on SPM. [Citation Graph (0, 0)][DBLP]
    ICESS, 2007, pp:174-180 [Conf]
  23. Tianzhou Chen, Like Yan, Bin Xie
    An implementation of power-aware storage architecture. [Citation Graph (0, 0)][DBLP]
    IWCMC, 2006, pp:1117-1122 [Conf]

  24. A Bypass Optimization Method for Network on Chip. [Citation Graph (, )][DBLP]


  25. Promoting Multi-Core Education via Special Training and Workshop Program. [Citation Graph (, )][DBLP]


  26. Smartphone Software Development Course Design Based on Android. [Citation Graph (, )][DBLP]


  27. On-Chip Operating System Design for NoC-Based CMP. [Citation Graph (, )][DBLP]


  28. Network Main Memory Architecture for NoC-Based Chips. [Citation Graph (, )][DBLP]


  29. Distributed On-Chip Operating System for Network on Chip. [Citation Graph (, )][DBLP]


  30. Virtual I/O Based on ScratchPad Memory for Embedded System. [Citation Graph (, )][DBLP]


  31. Global Register Alias Table: Executing Sequential Program on Multi-Core. [Citation Graph (, )][DBLP]


  32. Design of Teaching System for Computer Network Application Learning. [Citation Graph (, )][DBLP]


  33. An Efficient Power-Aware Optimization for Task Scheduling on NoC-based Many-core System. [Citation Graph (, )][DBLP]


  34. Augmenting NoC with Naming Service for Slot-based Reconfigurable Devices on Chip. [Citation Graph (, )][DBLP]


  35. Distributed Memory Management Units Architecture for NoC-based CMPs. [Citation Graph (, )][DBLP]


  36. A Reconfigurable Processor Architecture Combining Multi-core and Reconfigurable Processing Unit. [Citation Graph (, )][DBLP]


  37. Homogeneous NoC-based FPGA: The Foundation for Virtual FPGA. [Citation Graph (, )][DBLP]


  38. L1 Collective Cache: Managing Shared Data for Chip Multiprocessors. [Citation Graph (, )][DBLP]


  39. SPMTM: A Novel ScratchPad Memory Based Hybrid Nested Transactional Memory Framework. [Citation Graph (, )][DBLP]


  40. A Performance Model for Run-Time Reconfigurable Hardware Accelerator. [Citation Graph (, )][DBLP]


  41. Serial Application Accelerating with Pipelined Configuration Slicing on Dynamic Reconfigurable Hardware. [Citation Graph (, )][DBLP]


  42. eNSTM: a Nested Software Transactional Memory Framework for MPSoC System. [Citation Graph (, )][DBLP]


  43. Learning Support Service for Distance Learning Curriculum of Information Security. [Citation Graph (, )][DBLP]


  44. An Exploration Program for Undergraduate Research Training. [Citation Graph (, )][DBLP]


  45. The input-aware dynamic adaptation of area and performance for reconfigurable accelerator. [Citation Graph (, )][DBLP]


  46. Heterogeneous Multi-core Design for Information Retrieval Efficiency on the Vector Space Model. [Citation Graph (, )][DBLP]


  47. Multicore Challenge in Pervasive Computing Education. [Citation Graph (, )][DBLP]


  48. A fast algorithm for energy-aware mapping of cores onto WK-recursive NoC under performance constraints. [Citation Graph (, )][DBLP]


  49. Function Units Sharing between Neighbor Cores in CMP. [Citation Graph (, )][DBLP]


  50. Single Thread Program Parallelism with Dataflow Abstracting Thread. [Citation Graph (, )][DBLP]


  51. Embedded education for Computer Rank Examination. [Citation Graph (, )][DBLP]


  52. The Organization of Intel Cup Undergraduate Embedded System Electronic Design Contest. [Citation Graph (, )][DBLP]


  53. Adapting Experiments of Embedded System Curriculum Designed Based on Embedded IA to Atom. [Citation Graph (, )][DBLP]


  54. Less reused filter: improving l2 cache performance via filtering less reused lines. [Citation Graph (, )][DBLP]


  55. Power-Aware Code Restructuring for Embedded Parallel Storing Device. [Citation Graph (, )][DBLP]


  56. PZSPTF: Parallelism-aware and Zone-based Shortest Positioning TimeFirst Scheduling for MEMS-based Storage Devices. [Citation Graph (, )][DBLP]


  57. Efficient Utilization of Scratch-Pad Memory for Embedded Systems. [Citation Graph (, )][DBLP]


  58. Component-based Network Protocol Architecture for Multi-core. [Citation Graph (, )][DBLP]


  59. A Practical Dynamic Frequency Scaling Scheduling Algorithm for General Purpose Embedded Operating System. [Citation Graph (, )][DBLP]


  60. A Java Development Platform in Mobile System for Smart Home. [Citation Graph (, )][DBLP]


  61. Coordinating System Software for Power Savings. [Citation Graph (, )][DBLP]


  62. Development and calibration of a low cost wireless camera sensor network. [Citation Graph (, )][DBLP]


  63. Study of Heterogeneous Distributed Resource Warehouse Semantic Retrieving Based on Multi-agent. [Citation Graph (, )][DBLP]


  64. Experiences in Collaboration with Intel Corporation in Embedded Education. [Citation Graph (, )][DBLP]


  65. Online Programming Experience Platform for Multicore Curriculum. [Citation Graph (, )][DBLP]


  66. Model Curriculum Construction of Embedded System in Zhejiang University. [Citation Graph (, )][DBLP]


  67. Computer Ability Assisted Assessment System for Large-Scale Heterogeneous Distributed Environments. [Citation Graph (, )][DBLP]


  68. The Practice of Remote Education on Information Security. [Citation Graph (, )][DBLP]


  69. Introduction to the Reform on the Course of Fundamental Logic and Computer Design. [Citation Graph (, )][DBLP]


  70. Dynamic power management framework for multi-core portable embedded system. [Citation Graph (, )][DBLP]


  71. Program Sections Allocation to Scratchpad Memory based on Frequency Analysis. [Citation Graph (, )][DBLP]


  72. An On-chip Communication Mechanism Design in the Embedded Heterogeneous Multi-core Architecture. [Citation Graph (, )][DBLP]


  73. Exploring multicore computing education in China by model curriculum construction. [Citation Graph (, )][DBLP]


  74. Research for Data Mining Applying in the Architecture of Web-Learning. [Citation Graph (, )][DBLP]


  75. Optimistic Peripheral Devices Performance by Virtual Regionalized Network-on-Chip. [Citation Graph (, )][DBLP]


  76. The Implementation of a Mobile Java Debug Tool. [Citation Graph (, )][DBLP]


  77. The Design and Implementation of Adaptive Reconfigurable Computing Array. [Citation Graph (, )][DBLP]


  78. Efficient Scratchpad Memory Management Based on Multi-thread for MPSoC Architecture. [Citation Graph (, )][DBLP]


  79. A Tightly Coupled Network-on-Chip Router Architecture. [Citation Graph (, )][DBLP]


  80. ZELU: A Case Study of Computer Technology in Electronic Labour Union Construction in Zhejiang University. [Citation Graph (, )][DBLP]


  81. CMP Thread Assignment Based on Group Sharing L2 Cache. [Citation Graph (, )][DBLP]


  82. Online System Support for Computer Organization Course. [Citation Graph (, )][DBLP]


Search in 0.007secs, Finished in 0.009secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002