The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Gregory Malecha: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author


  1. Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability. [Citation Graph (, )][DBLP]


  2. Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions. [Citation Graph (, )][DBLP]


Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002