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Hyuk-Jae Lee:
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Publications of Author
- Genhua Jin, Hyuk-Jae Lee
A Parallel and Pipelined Execution of H.264/AVC Intra Prediction. [Citation Graph (0, 0)][DBLP] CIT, 2006, pp:246- [Conf]
- Dae-Hwan Kim, Hyuk-Jae Lee
Register Allocation Based on a Reference Flow Analysis. [Citation Graph (0, 0)][DBLP] APLAS, 2003, pp:394-409 [Conf]
- Hyuk-Jae Lee, José A. B. Fortes
Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms. [Citation Graph (0, 0)][DBLP] ASAP, 1995, pp:34-0 [Conf]
- Hyuk-Jae Lee, José A. B. Fortes
Automatic Generation of Modular Mappings. [Citation Graph (0, 0)][DBLP] ASAP, 1996, pp:155-164 [Conf]
- Dae-Hwan Kim, Hyuk-Jae Lee
Iterative procedural abstraction for code size reduction. [Citation Graph (0, 0)][DBLP] CASES, 2002, pp:277-279 [Conf]
- Hyuk-Jae Lee, José A. B. Fortes
Conditions of Blocked BLAS-like Algorithms for Data Alignment and Communication Minimization. [Citation Graph (0, 0)][DBLP] ICPP (3), 1995, pp:220-223 [Conf]
- Hyuk-Jae Lee, José A. B. Fortes
Automatic generation of injective modular mappings. [Citation Graph (0, 0)][DBLP] ICPP, 1997, pp:417-0 [Conf]
- Hyuk-Jae Lee, James P. Robertson, José A. B. Fortes
Generalized Cannon's Algorithm for Parallel Matrix Multiplication. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1997, pp:44-51 [Conf]
- Hyuk-Jae Lee, José A. B. Fortes
Toward data distribution independent parallel matrix multiplication. [Citation Graph (0, 0)][DBLP] IPPS, 1995, pp:436-440 [Conf]
- Dae-Hwan Kim, Hyuk-Jae Lee
Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors. [Citation Graph (0, 0)][DBLP] SAMOS, 2006, pp:269-278 [Conf]
- Dae-Hwan Kim, Hyuk-Jae Lee
Fine-Grain Register Allocation Based on a Global Spill Costs Analysis. [Citation Graph (0, 0)][DBLP] SCOPES, 2003, pp:255-269 [Conf]
- Hyuk-Jae Lee, José A. B. Fortes
Communication-Minimal Partitioning and Data Alignment for Affine Nested Loops. [Citation Graph (0, 0)][DBLP] Comput. J., 1997, v:40, n:6, pp:302-310 [Journal]
- Hyuk-Jae Lee, José A. B. Fortes
Modular Mappings and Data Distribution Independent Computations. [Citation Graph (0, 0)][DBLP] Parallel Processing Letters, 1997, v:7, n:2, pp:169-180 [Journal]
- Yukong Zhang, Young-Jun Kwon, Hyuk-Jae Lee
A Systematic Generation of Initial Register-Reuse Chains for Dependence Minimization. [Citation Graph (0, 0)][DBLP] SIGPLAN Notices, 2001, v:36, n:2, pp:47-54 [Journal]
- Hyuk-Jae Lee, José A. B. Fortes
Generation of Injective and Reversible Modular Mappings. [Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:1, pp:1-12 [Journal]
- Yongje Lee, Chae-Eun Rhee, Hyuk-Jae Lee
A New Frame Recompression Algorithm Integrated with H.264 Video Compression. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1621-1624 [Conf]
- Jin-Sung Kim, Hyuk-Jae Lee
A PDP Sub-field Coding Algorithm for the Reduction of Errors due to Line Load Variation. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:3419-3422 [Conf]
- Genhua Jin, Jin-Su Jung, Hyuk-Jae Lee
An Efficient Pipelined Architecture for H.264/AVC Intra Frame Processing. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1605-1608 [Conf]
- Ju-Hyun Kim, Gyoung-Hwan Hyun, Hyuk-Jae Lee
Cache Organizations for H.264/AVC Motion Compensation. [Citation Graph (0, 0)][DBLP] RTCSA, 2007, pp:534-541 [Conf]
Hardware/Software Partitioned Implementation of Real-time Object-oriented Camera for Arbitrary-shaped MPEG-4 Contents. [Citation Graph (, )][DBLP]
Block-Level Processing of a Video Object Segmentation Algorithm for Real-Time Systems. [Citation Graph (, )][DBLP]
Two-Bit Transform Based Block Motion Estimation using Second Derivatives. [Citation Graph (, )][DBLP]
An Edge-Adaptive Block Matching Algorithm for Error Concealment. [Citation Graph (, )][DBLP]
Speed control for a hardware based H.264/AVC encoder. [Citation Graph (, )][DBLP]
Fast pipeline schedule for an H.264 intra frame encoder with early termination. [Citation Graph (, )][DBLP]
A High-Speed Link Layer Architecture for Low Latency and Memory Cost Reduction. [Citation Graph (, )][DBLP]
A Phase-Based Approach for On-Chip Bus Architecture Optimization. [Citation Graph (, )][DBLP]
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