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Tomohiro Yoneda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
    ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. [Citation Graph (0, 0)][DBLP]
    CIT, 2006, pp:172- [Conf]
  2. Tomohiro Yoneda, Yutaka Ohtsuka, Märt Saarepera
    Verification of Parameterized Asynchronous Circuits: A Case Study. [Citation Graph (0, 0)][DBLP]
    ACSD, 1998, pp:64-74 [Conf]
  3. Tomohiro Yoneda, Bin Zhou, Bernd-Holger Schlingloff
    Verification of Bounded Delay Asynchronous Circuits with Timed Traces. [Citation Graph (0, 0)][DBLP]
    AMAST, 1998, pp:59-73 [Conf]
  4. Bin Zhou, Tomohiro Yoneda, Bernd-Holger Schlingloff
    Conformance and mirroring for timed asychronous circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:341-346 [Conf]
  5. Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers
    High Level Synthesis of Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2005, pp:178-189 [Conf]
  6. Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers
    Synthesis of Speed Independent Circuits Based on Decomposition. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:135-145 [Conf]
  7. Tomohiro Yoneda, Hiroshi Ryu
    Timed Trace Theoretic Verification Using Partial Order Reduction. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:108-0 [Conf]
  8. Märt Saarepera, Tomohiro Yoneda
    A Self-Timed Implementation of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1999, pp:243-0 [Conf]
  9. Bin Zhou, Tomohiro Yoneda, Chris J. Myers
    Framework of Timed Trace Theoretic Verification Revisited. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:437-442 [Conf]
  10. Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers
    Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ATVA, 2004, pp:339-353 [Conf]
  11. Tomohiro Yoneda, Chris J. Myers
    Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    ATVA, 2006, pp:229-244 [Conf]
  12. Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda
    Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. [Citation Graph (0, 0)][DBLP]
    ATVA, 2004, pp:426-440 [Conf]
  13. Tomohiro Yoneda
    VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    CAV, 2000, pp:572-575 [Conf]
  14. Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers
    Automatic Derivation of Timing Constraints by Failure Analysis. [Citation Graph (0, 0)][DBLP]
    CAV, 2002, pp:195-208 [Conf]
  15. Tomohiro Yoneda, Atsufumi Shibayama, Bernd-Holger Schlingloff, Edmund M. Clarke
    Efficient Verification of Parallel Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1993, pp:321-346 [Conf]
  16. Tomohiro Yoneda, Hideyuki Hatori, Atsushi Takahara, Shin-ichi Minato
    BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:435-449 [Conf]
  17. Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
    Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:424-432 [Conf]
  18. Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda
    Verification of analog/mixed-signal circuits using labeled hybrid petri nets. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:275-282 [Conf]
  19. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
    Verification of Timed Circuits with Failure Directed Abstractions. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:28-35 [Conf]
  20. Tomohiro Yoneda
    Verification of Abstracted Instruction Cache of TITAC2: A Case Study. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:373-384 [Conf]
  21. Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers
    Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:210-220 [Conf]
  22. Tomoya Kitai, Tomohiro Yoneda
    Partial Order Reduction in Verification of Wheel Structured Parameterized Circuits. [Citation Graph (0, 0)][DBLP]
    PRDC, 2001, pp:173-182 [Conf]
  23. Eric Mercer, Chris J. Myers, Tomohiro Yoneda
    Modular Synthesis of Timed Circuits using Partial Order Reduction. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal]
  24. Tomohiro Yoneda, Bernd-Holger Schlingloff
    Efficient Verification of Parallel Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:11, n:2, pp:187-215 [Journal]
  25. Koichi Masukura, Minoru Tomisaka, Tomohiro Yoneda
    Verification of asynchronous circuits based on zero-suppressed BDDs. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2001, v:32, n:2, pp:43-54 [Journal]
  26. Hiroshi Toshima, Tomohiro Yoneda
    Efficient verification by exploiting symmetry and abstraction. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2001, v:32, n:14, pp:41-53 [Journal]
  27. Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya
    Verification of asynchronous logic circuit design using process algebra. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:8-9, pp:33-43 [Journal]
  28. Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
    Verification of timed circuits with failure-directed abstractions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:403-412 [Journal]
  29. Frédéric Béal, Tomohiro Yoneda, Chris J. Myers
    Hazard Checking of Timed Asynchronous Circuits Revisited. [Citation Graph (0, 0)][DBLP]
    ACSD, 2007, pp:51-60 [Conf]

  30. A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). [Citation Graph (, )][DBLP]


  31. Asynchronous pipeline controller based on early acknowledgement protocol. [Citation Graph (, )][DBLP]


  32. Symbolic Model Checking of Analog/Mixed-Signal Circuits. [Citation Graph (, )][DBLP]


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