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Takashi Nanya: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
    ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. [Citation Graph (0, 0)][DBLP]
    CIT, 2006, pp:172- [Conf]
  2. Hiroto Kagotani, Takuji Okamoto, Takashi Nanya
    Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:425-430 [Conf]
  3. Mohit Sahni, Takashi Nanya
    On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:183-189 [Conf]
  4. Hiroshi Saito, Takashi Nanya, Alex Kondratyev
    Design of Asynchronous Controllers with Delay Insensitive Interface. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:93-98 [Conf]
  5. Nattha Sretasereekul, Takashi Nanya
    Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:437-442 [Conf]
  6. Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya
    TITAC-2: An Asynchronous 32-bit Microprocessor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:319-320 [Conf]
  7. Masashi Imai, Metehan Özcan, Takashi Nanya
    Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:62-71 [Conf]
  8. Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya
    Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:262-273 [Conf]
  9. Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno
    Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:162-172 [Conf]
  10. Metehan Özcan, Masashi Imai, Takashi Nanya
    Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:109-114 [Conf]
  11. Masashi Imai, Takashi Nanya
    A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:68-77 [Conf]
  12. Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
    Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:184-195 [Conf]
  13. Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya
    Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10276-10281 [Conf]
  14. Takashi Nanya, Shin'ichi Hatakenaka, Ryuichi Onoo
    Design of Fully Exercised SFS/SCD Logic Networks. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:96-103 [Conf]
  15. Stanislaw J. Piestrak, Takashi Nanya
    Towards Totally Self-Checking Delay-Insensitive Systems. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:228-237 [Conf]
  16. Andreas Savva, Takashi Nanya
    Gracefully Degrading Systems Using the Bulk-Synchronous Parallel Model with Randomised Shared Memory. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:299-308 [Conf]
  17. Wen Gao, Xinyu Liu, Lei Wang, Takashi Nanya
    A Reconfigurable High Availability Infrastructure in Cluster for Grid. [Citation Graph (0, 0)][DBLP]
    GCC (1), 2003, pp:576-583 [Conf]
  18. Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya
    TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:288-294 [Conf]
  19. Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
    Asynchronous Scan-Latch controller for Low Area Overhead DFT. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:66-71 [Conf]
  20. Elias Procópio Duarte Jr., Glenn Mansfield, Takashi Nanya, Shoichi Noguchi
    Non-Broadcast Network Fault-Monitoring Based on System-Level Diagnosis. [Citation Graph (0, 0)][DBLP]
    Integrated Network Management, 1997, pp:597-609 [Conf]
  21. Keqiu Li, Takashi Nanya, Bo Jiang, Wenyu Qu
    State-of-Art Techniques for Object Caching over the Internet. [Citation Graph (0, 0)][DBLP]
    IMSCCS (2), 2006, pp:199-206 [Conf]
  22. Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya
    Control signal sharing of asynchronous circuits using datapath delay information. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:617-620 [Conf]
  23. Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya
    A zero-time-overhead asynchronous four-phase controller. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:205-208 [Conf]
  24. Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya
    Logic Optimization for Asynchronous SI Controllers using Transduction Method. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:245-250 [Conf]
  25. Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
    High Throughput Asynchronous Domino Using Dual output Buffer. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:279-282 [Conf]
  26. Masayuki Tsukisaka, Takashi Nanya
    A testable design for asynchronous fine-grain pipeline circuits. [Citation Graph (0, 0)][DBLP]
    PRDC, 2000, pp:148-155 [Conf]
  27. Bogdan Tomoyuki Nassu, Takashi Nanya
    A Scenario of Tolerating Interaction Faults Between Otherwise Correct Systems. [Citation Graph (0, 0)][DBLP]
    PRDC, 2006, pp:371-372 [Conf]
  28. Elias Procópio Duarte Jr., Takashi Nanya
    Hierarchical Adaptive Distributed System-Level Diagnosis Applied for SNMP-based Network Fault Management. [Citation Graph (0, 0)][DBLP]
    Symposium on Reliable Distributed Systems, 1996, pp:98-107 [Conf]
  29. Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
    Skewed Checkpointing for Tolerating Multi-Node Failures. [Citation Graph (0, 0)][DBLP]
    SRDS, 2004, pp:116-125 [Conf]
  30. Sung-Bum Park, Takashi Nanya
    Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:389-392 [Conf]
  31. Hiroshi Saito, Alex Kondratyev, Takashi Nanya
    Design of Asynchronous Controllers with Delay Insensitive Interface. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:93-98 [Conf]
  32. Keqiu Li, Wenyu Qu, Hong Shen, Di Wu, Takashi Nanya
    Two Cache Replacement Algorithms Based on Association Rules and Markov Models. [Citation Graph (0, 0)][DBLP]
    SKG, 2005, pp:28- [Conf]
  33. Wenyu Qu, Keqiu Li, Hong Shen, Yingwei Jin, Takashi Nanya
    The Cache Replacement Problem for Multimedia Object Caching. [Citation Graph (0, 0)][DBLP]
    SKG, 2005, pp:26- [Conf]
  34. Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, Akihiro Takamura
    TITAC: Design of A Quasi-Delay-Insensitive Microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:2, pp:50-63 [Journal]
  35. Elias Procópio Duarte Jr., Glenn Mansfield, Takashi Nanya, Shoichi Noguchi
    Improving the dependability of network management systems. [Citation Graph (0, 0)][DBLP]
    Int. Journal of Network Management, 1998, v:8, n:4, pp:244-253 [Journal]
  36. Arthit Thongtak, Takashi Nanya
    Stuck-at-fault testing for quasi-delay-insensitive logic circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1998, v:29, n:2, pp:19-27 [Journal]
  37. Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya
    Verification of asynchronous logic circuit design using process algebra. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:8-9, pp:33-43 [Journal]
  38. Elias Procópio Duarte Jr., Takashi Nanya
    A Hierarachical Adaptive Distributed System-Level Diagnosis Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:1, pp:34-45 [Journal]
  39. Takashi Nanya, Toshiaki Kawamura
    A Note on Strongly Fault-Secure Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:9, pp:1121-1123 [Journal]
  40. Takashi Nanya, Toshiaki Kawamura
    On Error Indication for Totally Self-Checking Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:11, pp:1389-1392 [Journal]
  41. Takashi Nanya, Toshiaki Kawamura
    Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:1, pp:14-24 [Journal]
  42. Takashi Nanya, Yoshihiro Tohma
    On Universal Single Transition Time Asynchronous State Assignments. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:8, pp:781-782 [Journal]
  43. Takashi Nanya, Yoshihiro Tohma
    Universal Multicode STT State Assignments for Asynchronous Sequential Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1979, v:28, n:11, pp:811-818 [Journal]
  44. Andreas Savva, Takashi Nanya
    A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:1, pp:38-52 [Journal]
  45. Teruhiko Yamada, Takashi Nanya
    Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:8, pp:758-761 [Journal]
  46. Teruhiko Yamada, Takashi Nanya
    Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:5, pp:511-512 [Journal]
  47. Takashi Nanya, Hendrik A. Goosen
    The Byzantine hardware fault model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:11, pp:1226-1231 [Journal]
  48. Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
    Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:797-802 [Conf]
  49. Keqiu Li, Takashi Nanya, Wenyu Qu
    A Minimal Access Cost-Based Multimedia Object Replacement Algorithm. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-7 [Conf]
  50. Takashi Nanya
    Challenges in Dependability of Networked Systems for Information Society. [Citation Graph (0, 0)][DBLP]
    NPC, 2007, pp:542- [Conf]
  51. Wenyu Qu, Keqiu Li, Masaru Kitsuregawa, Takashi Nanya
    An optimal solution for caching multimedia objects in transcoding proxies. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2007, v:30, n:8, pp:1802-1810 [Journal]

  52. A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). [Citation Graph (, )][DBLP]


  53. A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. [Citation Graph (, )][DBLP]


  54. Injecting Inconsistent Values Caused by Interaction Faults for Experimental Dependability Evaluation. [Citation Graph (, )][DBLP]


  55. Analysis of Inter-Module Error Propagation Paths in Monolithic Operating System Kernels. [Citation Graph (, )][DBLP]


  56. An Efficient Method for Improving Data Collection Precision in Lifetime-adaptive Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  57. Power reduction of chip multi-processors using shared resource control cooperating with DVFS. [Citation Graph (, )][DBLP]


  58. Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values. [Citation Graph (, )][DBLP]


  59. Interaction Faults Caused by Third-Party External Systems - A Case Study and Challenges. [Citation Graph (, )][DBLP]


  60. Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies. [Citation Graph (, )][DBLP]


  61. Limitations of the Linux Fault Injection Framework to Test Direct Memory Access Address Errors. [Citation Graph (, )][DBLP]


  62. Zapmem: A Framework for Testing the Effect of Memory Corruption Errors on Operating System Kernel Reliability. [Citation Graph (, )][DBLP]


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