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Oliver Rose: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Oliver Rose, Michael R. Frater
    A Comparison of Models for VBR Video Traffic Sources in B-ISDN. [Citation Graph (0, 0)][DBLP]
    Broadband Communications, 1994, pp:275-287 [Conf]
  2. John W. Fowler, Barry L. Nelson, Michael Pinedo, Oliver Rose
    05281 Executive Summary - Simulation & Scheduling: Companions or Competitors for Improving the Performance of Manufacturing Systems. [Citation Graph (0, 0)][DBLP]
    Simulation & Scheduling, 2005, pp:- [Conf]
  3. John W. Fowler, Barry L. Nelson, Michael Pinedo, Oliver Rose
    05281 Abstracts Collection - Simulation & Scheduling: Companions or Competitors for Improving the Performance of Manufacturing Systems. [Citation Graph (0, 0)][DBLP]
    Simulation & Scheduling, 2005, pp:- [Conf]
  4. Oliver Rose, Michael R. Frater
    Impact of MPEG video traffic on an ATM Multiplexer. [Citation Graph (0, 0)][DBLP]
    HPN, 1995, pp:157-168 [Conf]
  5. Oliver Rose
    Traffic Modeling of Variable Bit Rate MPEG Video and Its Impacts on ATM Networks. [Citation Graph (0, 0)][DBLP]
    Kommunikation in Verteilten Systemen, 1999, pp:514-519 [Conf]
  6. Oliver Rose
    Statistical properties of MPEG video traffic and their impact on traffic modeling in ATM systems. [Citation Graph (0, 0)][DBLP]
    LCN, 1995, pp:397-406 [Conf]
  7. Simon Oechsner, Oliver Rose
    Scheduling cluster tools using filtered beam search and recipe comparison. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 2005, pp:2203-2210 [Conf]
  8. Oliver Rose
    General simulation applications in semiconductor manufacturing: why do simple wafer fab models fail in certain scenarios? [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 2000, pp:1481-1490 [Conf]
  9. Oliver Rose
    Modeling methodology: the shortest processing time first (SPTF) dispatch rule and some variants in semiconductor manufacturing. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 2001, pp:1220-1224 [Conf]
  10. Oliver Rose
    Scheduling and dispatching: some issues of the critical ratio dispatch rule in semiconductor manufacturing. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 2002, pp:1401-1405 [Conf]
  11. Oliver Rose
    Factory scheduling and dispatching: accelerating products under due-date oriented dispatching rules in semiconductor manufacturing. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 2003, pp:1346-1350 [Conf]
  12. Oliver Rose
    Modeling Tool Failures in Semiconductor Fab Simulation. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 2004, pp:1910-0 [Conf]
  13. Oliver Rose
    WIP Evolution of a Semiconductor Factory after a Bottleneck Workcenter Breakdown. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 1998, pp:997-1004 [Conf]
  14. Oliver Rose
    CONLOAD - a new lot release rule for semiconductor wafer fabs. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 1999, pp:850-855 [Conf]
  15. Robert Unbehaun, Oliver Rose
    The use of slow down factors for the analysis and development of scheduling algorithms for parallel cluster tools. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 2006, pp:1840-1847 [Conf]
  16. Kilian Schmidt, Jörg Weigang, Oliver Rose
    Modeling semiconductor tools for small lotsize FAB simulations. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 2006, pp:1811-1816 [Conf]
  17. Oliver Rose
    Economy of scale effects for large wafer fabs. [Citation Graph (0, 0)][DBLP]
    Winter Simulation Conference, 2006, pp:1817-1820 [Conf]
  18. Oliver Rose
    Simple and Efficient Models for Variable Bit Rate MPEG Video Traffic. [Citation Graph (0, 0)][DBLP]
    Perform. Eval., 1997, v:30, n:1-2, pp:69-85 [Journal]
  19. Oliver Rose
    Implementation of a Simulation-Based Optimizer for Semiconductor Wafer Factories. [Citation Graph (0, 0)][DBLP]
    ETFA, 2006, pp:943-949 [Conf]

  20. Improved simple simulation models for semiconductor wafer factories. [Citation Graph (, )][DBLP]


  21. Predicting cluster tool behavior with slow down factors. [Citation Graph (, )][DBLP]


  22. Automated generation and parameterization of throughput models for semiconductor tools. [Citation Graph (, )][DBLP]


  23. A simulation based optimization algorithm for slack reduction and workforce scheduling. [Citation Graph (, )][DBLP]


  24. Simulation analysis of semiconductor manufacturing with small lot size and batch tool replacements. [Citation Graph (, )][DBLP]


  25. An optimization framework for waferfab performance enhancement. [Citation Graph (, )][DBLP]


  26. A Bottleneck Detection and Dynamic Dispatching Strategy for Semiconductor Wafer Fabrication Facilities. [Citation Graph (, )][DBLP]


  27. Are Simulation Standards in our Future? [Citation Graph (, )][DBLP]


  28. First Steps Towards a General SysML Model for Discrete Processes in Production Systems. [Citation Graph (, )][DBLP]


  29. Evaluation of Modeling, Simulation and Optimization Approaches for Work Flow Management in Semiconductor Manufacturing. [Citation Graph (, )][DBLP]


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