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Xiaowei Li: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lei Xie, Yongjun Xu, Xiaowei Li, Yuefei Zhu
    A Lightweight Scheme for Trust Relationship Establishment in Ubiquitous Sensor Networks. [Citation Graph (0, 0)][DBLP]
    CIT, 2006, pp:229- [Conf]
  2. Hongyang Chen, Deng Ping, Yongjun Xu, Xiaowei Li
    A Novel Localization Scheme Based on RSS Data for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    APWeb Workshops, 2006, pp:315-320 [Conf]
  3. Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li
    Design of an efficient memory subsystem for network processor. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:897-900 [Conf]
  4. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
    Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:53-58 [Conf]
  5. Xiaowei Li, Paul Y. S. Cheung
    Data Path Synthesis for BIST with Low Area Overhead. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:275-278 [Conf]
  6. Yongjun Xu, Jinghua Chen, Zuying Luo, Xiaowei Li
    Vector extraction for average total power estimation. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1086-1089 [Conf]
  7. Xiaowei Li, Paul Y. S. Cheung
    Exploiting BIST Approach for Two-Pattern Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:424-429 [Conf]
  8. Guanghui Li, Xiaowei Li
    Circuit-Width Based Heuristic for Boolean Reasoning. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:336-341 [Conf]
  9. Yunzhan Gong, Wanli Xu, Xiaowei Li
    An Expression's Single Fault Model and the Testing Methods. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:110-115 [Conf]
  10. Guangmei Zhang, Chen Rui, Xiaowei Li, Han Congying
    The Automatic Generation of Basis Set of Path for Path Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:46-51 [Conf]
  11. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Rapid and Energy-Efficient Testing for Embedded Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:8-13 [Conf]
  12. Yinhe Han, Xiaowei Li, Shivakumar Swaminathan, Yu Hu, Anshuman Chandra
    Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:372-377 [Conf]
  13. Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:440-445 [Conf]
  14. Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li
    Pair Balance-Based Test Scheduling for SOCs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:236-241 [Conf]
  15. Guangyan Huang, Guangmei Zhang, Xiaowei Li, Yunzhan Gong
    A State Machine for Detecting C/C++ Memory Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:82-87 [Conf]
  16. Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara
    Strong self-testability for data paths high-level synthesis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:229-234 [Conf]
  17. Guanghui Li, Ming Shao, Xiaowei Li
    Design Error Diagnosis Based on Verification Techniques. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:474-477 [Conf]
  18. Huawei Li, Yue Zhang, Xiaowei Li
    Delay Test Pattern Generation Considering Crosstalk-Induced Effects. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:178-183 [Conf]
  19. Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min
    Test Power Optimization Techniques for CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:332-337 [Conf]
  20. Tao Lv, Jianping Fan, Xiaowei Li
    An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:161-167 [Conf]
  21. Ming Shao, Guanghui Li, Xiaowei Li
    SAT-Based Algorithm of Verification for Port Order Fault. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:478-481 [Conf]
  22. Pei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li
    Non-robust Test Generation for Crosstalk-Induced Delay Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:120-125 [Conf]
  23. Yongjun Xu, Zuying Luo, Zhiguo Chen, Xiaowei Li
    Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:196-201 [Conf]
  24. Zhigang Yin, Yinghua Min, Xiaowei Li
    An Approach to RTL Fault Extraction and Test Generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:219-224 [Conf]
  25. Yinhe Han, Xiaowei Li
    Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test. [Citation Graph (0, 0)][DBLP]
    ESA/VLSI, 2004, pp:374-381 [Conf]
  26. Xiaowei Li, Paul Y. S. Cheung
    High-Level BIST Synthesis for Delay Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 1998, pp:318-0 [Conf]
  27. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra
    Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:298-305 [Conf]
  28. Xiaowei Li, Huawei Li, Yinghua Min
    Reducing Power Dissipation during At-Speed Test Application. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:116-0 [Conf]
  29. Dan Hou, Xia Shen, Xiaowei Li, Yue Liu, Yongtian Wang
    Digital Restoration of Historical Heritage by Reconstruction from Uncalibrated Images. [Citation Graph (0, 0)][DBLP]
    Edutainment, 2006, pp:1377-1382 [Conf]
  30. Xiaowei Li, Paul Y. S. Cheung
    Exploiting Test Resource Optimization in Data Path Synthesis for BIST. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:342-343 [Conf]
  31. Guangyan Huang, Xiaowei Li, Jing He
    Clustering Versus Evenly Distributing Energy Dissipation in Wireless Sensor Routing for Prolonging Network Lifetime. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (2), 2006, pp:1069-1072 [Conf]
  32. Xiaowei Li, Yue Liu, Yongtian Wang, Dayuan Yan, Dongdong Weng, Tao Yang
    An Improved Colored-Marker Based Registration Method for AR Applications. [Citation Graph (0, 0)][DBLP]
    ICCSA (3), 2005, pp:266-273 [Conf]
  33. Ji Li, Yinhe Han, Xiaowei Li
    Deterministic and low power BIST based on scan slice overlapping. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5670-5673 [Conf]
  34. Yanzhuo Tan, Yinhe Han, Xiaowei Li, Feiyin Lu, Yuchuan Chen
    Validation analysis and test flow optimization of VLSI chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5666-5669 [Conf]
  35. Xiaowei Li, Paul Y. S. Cheung
    An approach to behavioral synthesis for loop-based BIST. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:374-377 [Conf]
  36. Yongjun Xu, Zuying Luo, Xiaowei Li
    A maximum total leakage current estimation method. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:757-760 [Conf]
  37. Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li
    Using MUXs Network to Hide Bunches of Scan Chains. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:238-243 [Conf]
  38. Yu Hu, Xiaowei Li, Huawei Li, Xiao-Qing Wen
    Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. [Citation Graph (0, 0)][DBLP]
    PRDC, 2005, pp:175-182 [Conf]
  39. Huawei Li, Pei-Fu Shen, Xiaowei Li
    Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:300-305 [Conf]
  40. Xiaowei Li
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:1, pp:68-0 [Journal]
  41. Xiaowei Li, Paul Y. S. Cheung
    Exploiting Deterministic TPG for Path Delay Testing. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2000, v:15, n:5, pp:472-479 [Journal]
  42. Xiaowei Li
    Perface. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:145-145 [Journal]
  43. Xiaowei Li, Paul Y. S. Cheung
    High Level Synthesis for Loop-Based BIST. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2000, v:15, n:4, pp:338-345 [Journal]
  44. Xiaowei Li, Paul Y. S. Cheung
    A Loop-Based Apparatus for At-Speed Self-Testing. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2001, v:16, n:3, pp:278-285 [Journal]
  45. Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra
    Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:2, pp:201-209 [Journal]
  46. Xiaowei Li, Guanghui Li, Ming Shao
    Formal Verification Techniques Based on Boolean Satisfiability Problem. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2005, v:20, n:1, pp:38-47 [Journal]
  47. Zhigang Yin, Yinghua Min, Xiaowei Li, Huawei Li
    A Novel RT-Level Behavioral Description Based ATPG Method. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2003, v:18, n:3, pp:308-317 [Journal]
  48. Yongjun Xu, Zuying Luo, Xiaowei Li, Li-Jian Li, Xianlong Hong
    Leakage Current Estimation of CMOS Circuit with Stack Effect. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2004, v:19, n:5, pp:708-717 [Journal]
  49. Lei Zhang, Huawei Li, Xiaowei Li
    A Routing Algorithm for Random Error Tolerance in Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    HCI (4), 2007, pp:1210-1219 [Conf]
  50. Jie Don, Yu Hu, Yinhe Han, Xiaowei Li
    An on-chip combinational decompressor for reducing test data volume. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  51. Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han
    Fast Packet Classification using Group Bit Vector. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]
  52. Wei Wang, Yu Hu, Yinhe Han, Xiaowei Li, You-Sheng Zhang
    Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2007, v:22, n:5, pp:673-680 [Journal]
  53. Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra
    Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:531-540 [Journal]
  54. Huawei Li, Xiaowei Li
    Selection of Crosstalk-Induced Faults in Enhanced Delay Test. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:2, pp:181-195 [Journal]
  55. Tao Lv, Jianping Fan, Xiaowei Li, Ling-Yi Liu
    Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:3, pp:273-285 [Journal]

  56. A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. [Citation Graph (, )][DBLP]


  57. On reducing both shift and capture power for scan-based testing. [Citation Graph (, )][DBLP]


  58. Robust test generation for power supply noise induced path delay faults. [Citation Graph (, )][DBLP]


  59. M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. [Citation Graph (, )][DBLP]


  60. A Low Overhead On-Chip Path Delay Measurement Circuit. [Citation Graph (, )][DBLP]


  61. Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power. [Citation Graph (, )][DBLP]


  62. 3D model matching with Viewpoint-Invariant Patches (VIP). [Citation Graph (, )][DBLP]


  63. Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology. [Citation Graph (, )][DBLP]


  64. iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing. [Citation Graph (, )][DBLP]


  65. A unified online Fault Detection scheme via checking of Stability Violation. [Citation Graph (, )][DBLP]


  66. Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. [Citation Graph (, )][DBLP]


  67. An abstraction-guided simulation approach using Markov models for microprocessor verification. [Citation Graph (, )][DBLP]


  68. Diagnosis of multiple arbitrary faults with mask and reinforcement effect. [Citation Graph (, )][DBLP]


  69. Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. [Citation Graph (, )][DBLP]


  70. IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults. [Citation Graph (, )][DBLP]


  71. An on-chip clock generation scheme for faster-than-at-speed delay testing. [Citation Graph (, )][DBLP]


  72. Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. [Citation Graph (, )][DBLP]


  73. A Scan-Based Delay Test Method for Reduction of Overtesting. [Citation Graph (, )][DBLP]


  74. Adaptive Diagnostic Pattern Generation for Scan Chains. [Citation Graph (, )][DBLP]


  75. Static Crosstalk Noise Analysis with Transition Map. [Citation Graph (, )][DBLP]


  76. A Case Study on At-Speed Testing for a Gigahertz Microprocessor. [Citation Graph (, )][DBLP]


  77. Modeling and Recognition of Landmark Image Collections Using Iconic Scene Graphs. [Citation Graph (, )][DBLP]


  78. EEG: A Way to Explore Learner's Affect in Pervasive Learning Systems. [Citation Graph (, )][DBLP]


  79. On capture power-aware test data compression for scan-based testing. [Citation Graph (, )][DBLP]


  80. Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. [Citation Graph (, )][DBLP]


  81. MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency. [Citation Graph (, )][DBLP]


  82. Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy. [Citation Graph (, )][DBLP]


  83. Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures. [Citation Graph (, )][DBLP]


  84. Impact of Hazards on Pattern Selection for Small Delay Defects. [Citation Graph (, )][DBLP]


  85. A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. [Citation Graph (, )][DBLP]


  86. Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. [Citation Graph (, )][DBLP]


  87. Improving complex distributed software system availability through information hiding. [Citation Graph (, )][DBLP]


  88. Multiple Coupling Effects Oriented Path Delay Test Generation. [Citation Graph (, )][DBLP]


  89. Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. [Citation Graph (, )][DBLP]


  90. A sensor network performance inference algorithm based on passive measurement. [Citation Graph (, )][DBLP]


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