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Luc J. M. Claesen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ronny Martens, Luc J. M. Claesen
    An Evaluation of Different Handwriting Observation Techniques from a Signature Verification Point of View. [Citation Graph (0, 0)][DBLP]
    BSDIA, 1997, pp:273-282 [Conf]
  2. Stefan Hendricx, Luc J. M. Claesen
    Verification of Finite-State-Machine Refinements Using a Symbolic Methodology. [Citation Graph (0, 0)][DBLP]
    CHARME, 1999, pp:326-329 [Conf]
  3. Ivo Bolsens, W. De Rammelaere, Luc J. M. Claesen, Hugo De Man
    Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:513-518 [Conf]
  4. Patrick Odent, Luc J. M. Claesen, Hugo De Man
    Feedback Loops and Large Subcircuits in the Multiprocessor Implementation of a Relaxation Based Circuit Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:25-30 [Conf]
  5. S. Perremans, Luc J. M. Claesen, Hugo De Man
    Static Timing Analysis of Dynamically Sensitizable Paths. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:568-573 [Conf]
  6. Paul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De Man
    An intelligent module generator environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:730-735 [Conf]
  7. Stefan Hendricx, Luc J. M. Claesen
    Formally Verified Redundancy Removal. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:150-0 [Conf]
  8. Stefan Hendricx, Luc J. M. Claesen
    Symbolic Multi-Level Verification of Refinement. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:288-291 [Conf]
  9. Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Peeters
    Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:610-613 [Conf]
  10. Mark Genoe, Luc J. M. Claesen, Hugo De Man
    A Parallel Method for Functional Verification of Medium and High Throughput DSP Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:460-463 [Conf]
  11. Mark Genoe, Luc J. M. Claesen, Eric Verlind, Frank Proesmans, Hugo De Man
    Illustration of the SFG-Tracing Multi-Level Behavioral Verification Methodology, by the Correctness Proof of a High to Low Level Synthesis Application in CATHEDRAL-II. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:338-341 [Conf]
  12. Olivier Thiry, Luc J. M. Claesen
    A formal verification technique for embedded software. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:352-357 [Conf]
  13. Ronny Martens, Luc J. M. Claesen
    Dynamic Programming Optimisation for On-line Signature Verificatio. [Citation Graph (0, 0)][DBLP]
    ICDAR, 1997, pp:653-656 [Conf]
  14. Ronny Martens, Luc J. M. Claesen
    On-line Signature Verification: Discrimination Emphasised. [Citation Graph (0, 0)][DBLP]
    ICDAR, 1997, pp:657-660 [Conf]
  15. P. Johannes, Luc J. M. Claesen, Hugo De Man
    Performance Through Hierarchy in Static Timing Verification. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (1), 1992, pp:703-709 [Conf]
  16. Diederik Verkest, Luc J. M. Claesen, Hugo De Man
    A Proof of the Non-Restoring Division Algorithm and its Implementation on the Cathedral-II ALU. [Citation Graph (0, 0)][DBLP]
    Designing Correct Circuits, 1992, pp:173-192 [Conf]
  17. Diederik Verkest, J. Vandenbergh, Luc J. M. Claesen, Hugo De Man
    A Description Methodology for Parameterized Modules in the Boyer-Moore Logic. [Citation Graph (0, 0)][DBLP]
    TPCD, 1992, pp:37-57 [Conf]
  18. Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
    The Formal Semantics Definition of a Multi-Rate DSP Specification Language in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:375-394 [Conf]
  19. Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
    Degrees of Formality in Shallow Embedding Hardware Description Languages in HOL. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:89-100 [Conf]
  20. Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
    Reasoning About a Class of Linear Systems of Equations in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1994, pp:33-48 [Conf]
  21. Catia M. Angelo, Diederik Verkest, Luc J. M. Claesen, Hugo De Man
    Formal Hardware Verification in HOL and in Boyer-Moore: A Comparative Analysis. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:340-347 [Conf]
  22. W. Ploegaerts, Luc J. M. Claesen, Hugo De Man
    Defining Recursive Functions in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:358-366 [Conf]
  23. Luc J. M. Claesen
    ED&TC 1995: Simulation versus formal verification. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:2, pp:82-0 [Journal]
  24. Catia M. Angelo, Luc J. M. Claesen, Hugo De Man
    Modeling Multi-rate DSP Specification Semantics for Formal Transformational Design in HOL. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:5, n:1/2, pp:61-94 [Journal]
  25. Catia M. Angelo, Diederik Verkest, Luc J. M. Claesen, Hugo De Man
    On the Comparison of HOL and Boyer-Moore for Formal Hardware Verification. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1993, v:2, n:1, pp:45-72 [Journal]
  26. Diederik Verkest, Luc J. M. Claesen, Hugo De Man
    A Proof of the Nonrestoring Division Algorithm and its Implementation on an ALU. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:4, n:1, pp:5-31 [Journal]
  27. Ronny Martens, Luc J. M. Claesen
    Incorporating local consistency information into the online signature verification process. [Citation Graph (0, 0)][DBLP]
    IJDAR, 1998, v:1, n:2, pp:110-115 [Journal]
  28. Jacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man
    Timing verification using statically sensitizable paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:10723-10784 [Journal]
  29. Patrick Odent, Luc J. M. Claesen, Hugo De Man
    Acceleration of relaxation-based circuit simulation using a multiprocessor system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:1063-1072 [Journal]

  30. A symbolic core approach to the formal verification of integrated mixed-mode applications. [Citation Graph (, )][DBLP]


  31. SPI: an open interface integrating highly interactive electronic CAD tools. [Citation Graph (, )][DBLP]


  32. A combined waveform relaxation: waveform relaxation newton algorithm for efficient parallel circuit simulation. [Citation Graph (, )][DBLP]


  33. SLOCOP-II: a versatile timing verification system for MOSVLSI. [Citation Graph (, )][DBLP]


  34. Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment. [Citation Graph (, )][DBLP]


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