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Roope Kaivola: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Roope Kaivola
    Axiomatising Extended Computation Tree Logic. [Citation Graph (0, 0)][DBLP]
    CAAP, 1996, pp:87-101 [Conf]
  2. Roope Kaivola
    Formal Verification of Pentium® 4 Components with Symbolic Simulation and Inductive Invariants. [Citation Graph (0, 0)][DBLP]
    CAV, 2005, pp:170-184 [Conf]
  3. Roope Kaivola
    Compositional Model Checking for Linear-Time Temporal Logic. [Citation Graph (0, 0)][DBLP]
    CAV, 1992, pp:248-259 [Conf]
  4. Roope Kaivola
    Using Compositional Preorders in the Verification of Sliding Window Protocal. [Citation Graph (0, 0)][DBLP]
    CAV, 1997, pp:48-59 [Conf]
  5. Roope Kaivola, Katherine R. Kohatsu
    Proof Engineering in the Large: Formal Verification of Pentium® 4 Floating-Point Divider. [Citation Graph (0, 0)][DBLP]
    CHARME, 2001, pp:196-211 [Conf]
  6. Roope Kaivola
    Axiomatising Linear Time Mu-calculus. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1995, pp:423-437 [Conf]
  7. Roope Kaivola, Antti Valmari
    Using Truth-Preserving Reductions to Improve the Clarity of Kripke-Models. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1991, pp:361-375 [Conf]
  8. Roope Kaivola, Antti Valmari
    The Weakest Compositional Semantic Equivalence Preserving Nexttime-less Linear temporal Logic. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1992, pp:207-221 [Conf]
  9. Mark Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger
    Formal verification of iterative algorithms in microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:201-206 [Conf]
  10. Roope Kaivola, Naren Narasimhan
    Formal Verification of the Pentium ® 4 Floating-Point Multiplier. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:20-27 [Conf]
  11. Roope Kaivola
    Fixpoints for Rabin Tree Automata Make Complementation Easy. [Citation Graph (0, 0)][DBLP]
    ICALP, 1996, pp:312-323 [Conf]
  12. Roope Kaivola, Mark Aagaard
    Divider Circuit Verification with Model Checking and Theorem Proving. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 2000, pp:338-355 [Conf]
  13. T. Karvi, Tienari Tienari, Roope Kaivola
    Stepwise Development of Process-Algebraic Specifications in Decorated Trace Semantics. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2005, v:26, n:3, pp:293-317 [Journal]
  14. Roope Kaivola
    On Modal mu-Calculus and Büchi Tree Automata. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1995, v:54, n:1, pp:17-22 [Journal]
  15. Roope Kaivola, Katherine R. Kohatsu
    Proof engineering in the large: formal verification of Pentium?4 floating-point divider. [Citation Graph (0, 0)][DBLP]
    STTT, 2003, v:4, n:3, pp:323-334 [Journal]
  16. Roope Kaivola
    Axiomatising Extended Computation Tree Logic. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1998, v:190, n:1, pp:41-60 [Journal]

  17. Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation. [Citation Graph (, )][DBLP]

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