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## Search the dblp DataBase
Panagiotis Manolios:
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## Publications of Author- Panagiotis Manolios, Daron Vroon
**Algorithms for Ordinal Arithmetic.**[Citation Graph (0, 0)][DBLP] CADE, 2003, pp:243-257 [Conf] - Panagiotis Manolios, Kedar S. Namjoshi, Robert Summers
**Linking Theorem Proving and Model-Checking with Well-Founded Bisimulation.**[Citation Graph (0, 0)][DBLP] CAV, 1999, pp:369-379 [Conf] - Panagiotis Manolios, Daron Vroon
**Termination Analysis with Calling Context Graphs.**[Citation Graph (0, 0)][DBLP] CAV, 2006, pp:401-414 [Conf] - Panagiotis Manolios
**A Compositional Theory of Refinement for Branching Time.**[Citation Graph (0, 0)][DBLP] CHARME, 2003, pp:304-318 [Conf] - Panagiotis Manolios, Sudarshan K. Srinivasan
**A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems.**[Citation Graph (0, 0)][DBLP] CHARME, 2005, pp:363-366 [Conf] - Yuan Yu, Panagiotis Manolios, Leslie Lamport
**Model Checking TLA**[Citation Graph (0, 0)][DBLP]^{+}Specifications. CHARME, 1999, pp:54-66 [Conf] - Roma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan
**Monolithic verification of deep pipelines with collapsed flushing.**[Citation Graph (0, 0)][DBLP] DATE, 2006, pp:1234-1239 [Conf] - Panagiotis Manolios, Sudarshan K. Srinivasan
**Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:168-175 [Conf] - Panagiotis Manolios, Sudarshan K. Srinivasan
**Refinement Maps for Efficient Verification of Processor Models.**[Citation Graph (0, 0)][DBLP] DATE, 2005, pp:1304-1309 [Conf] - Panagiotis Manolios
**Correctness of Pipelined Machines.**[Citation Graph (0, 0)][DBLP] FMCAD, 2000, pp:161-178 [Conf] - Panagiotis Manolios, Daron Vroon
**Integrating Reasoning About Ordinal Arithmetic into ACL2.**[Citation Graph (0, 0)][DBLP] FMCAD, 2004, pp:82-97 [Conf] - Peter C. Dillinger, Panagiotis Manolios
**Bloom Filters in Probabilistic Verification.**[Citation Graph (0, 0)][DBLP] FMCAD, 2004, pp:367-381 [Conf] - Panagiotis Manolios, Sudarshan K. Srinivasan
**Verification of executable pipelined machines with bit-level interfaces.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:855-862 [Conf] - Panagiotis Manolios, Sudarshan K. Srinivasan
**A complete compositional reasoning framework for the efficient verification of pipelined machines.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:863-870 [Conf] - Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon
**Automatic memory reductions for RTL model verification.**[Citation Graph (0, 0)][DBLP] ICCAD, 2006, pp:786-793 [Conf] - Panagiotis Manolios, Daron Vroon
**Integrating static analysis and general-purpose theorem proving for termination analysis.**[Citation Graph (0, 0)][DBLP] ICSE, 2006, pp:873-876 [Conf] - Panagiotis Manolios, Richard J. Trefler
**Safety and Liveness in Branching Time.**[Citation Graph (0, 0)][DBLP] LICS, 2001, pp:366-0 [Conf] - Panagiotis Manolios, Sudarshan K. Srinivasan
**A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines.**[Citation Graph (0, 0)][DBLP] MEMOCODE, 2005, pp:188-197 [Conf] - Panagiotis Manolios
**Brief announcement: branching time refinement.**[Citation Graph (0, 0)][DBLP] PODC, 2003, pp:334- [Conf] - Panagiotis Manolios, Richard J. Trefler
**A lattice-theoretic characterization of safety and liveness.**[Citation Graph (0, 0)][DBLP] PODC, 2003, pp:325-333 [Conf] - Panagiotis Manolios, Yimin Zhang
**Implementing Survey Propagation on Graphics Processing Units.**[Citation Graph (0, 0)][DBLP] SAT, 2006, pp:311-324 [Conf] - William G. J. Halfond, Alessandro Orso, Panagiotis Manolios
**Using positive tainting and syntax-aware evaluation to counter SQL injection attacks.**[Citation Graph (0, 0)][DBLP] SIGSOFT FSE, 2006, pp:175-185 [Conf] - Peter C. Dillinger, Panagiotis Manolios
**Fast and Accurate Bitstate Verification for SPIN.**[Citation Graph (0, 0)][DBLP] SPIN, 2004, pp:57-75 [Conf] - Peter C. Dillinger, Panagiotis Manolios
**Enhanced Probabilistic Verification with 3Spin and 3Murphi.**[Citation Graph (0, 0)][DBLP] SPIN, 2005, pp:272-276 [Conf] - Peter C. Dillinger, Panagiotis Manolios, Daron Vroon, J. Strother Moore
**ACL2s: "The ACL2 Sedan".**[Citation Graph (0, 0)][DBLP] Electr. Notes Theor. Comput. Sci., 2007, v:174, n:2, pp:3-18 [Journal] - Panagiotis Manolios, J. Strother Moore
**On the desirability of mechanizing calculational proofs.**[Citation Graph (0, 0)][DBLP] Inf. Process. Lett., 2001, v:77, n:2-4, pp:173-179 [Journal] - Panagiotis Manolios, J. Strother Moore
**Partial Functions in ACL2.**[Citation Graph (0, 0)][DBLP] J. Autom. Reasoning, 2003, v:31, n:2, pp:107-127 [Journal] - Panagiotis Manolios, Sudarshan K. Srinivasan
**A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures.**[Citation Graph (0, 0)][DBLP] J. Autom. Reasoning, 2006, v:37, n:1-2, pp:93-116 [Journal] - Panagiotis Manolios, Daron Vroon
**Ordinal Arithmetic: Algorithms and Mechanization.**[Citation Graph (0, 0)][DBLP] J. Autom. Reasoning, 2005, v:34, n:4, pp:387-423 [Journal] - Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon
**BAT: The Bit-Level Analysis Tool.**[Citation Graph (0, 0)][DBLP] CAV, 2007, pp:303-306 [Conf] - Peter C. Dillinger, Panagiotis Manolios, Daron Vroon, J. Strother Moore
**ACL2s: "The ACL2 Sedan".**[Citation Graph (0, 0)][DBLP] ICSE Companion, 2007, pp:59-60 [Conf] - Panagiotis Manolios, Daron Vroon, Gayatri Subramanian
**Automating component-based system assembly.**[Citation Graph (0, 0)][DBLP] ISSTA, 2007, pp:61-72 [Conf] - Panagiotis Manolios, Daron Vroon
**Efficient Circuit to CNF Conversion.**[Citation Graph (0, 0)][DBLP] SAT, 2007, pp:4-9 [Conf] - Panagiotis Manolios
**Refinement and Theorem Proving.**[Citation Graph (0, 0)][DBLP] SFM, 2006, pp:176-210 [Conf] - Panagiotis Manolios, Marc Galceran Oms, Sergi Oliva Valls
**Checking Pedigree Consistency with PCS.**[Citation Graph (0, 0)][DBLP] TACAS, 2007, pp:339-342 [Conf] **Faster SAT solving with better CNF generation.**[Citation Graph (, )][DBLP]**Fast, All-Purpose State Storage.**[Citation Graph (, )][DBLP]**All-Termination(T).**[Citation Graph (, )][DBLP]**A PosterioriSoundness for Non-deterministic Abstract Interpretations.**[Citation Graph (, )][DBLP]**Generating High-Quality Tests for Boolean Circuits by Treating Tests as Proof Encoding.**[Citation Graph (, )][DBLP]**The Challenge of Hardware-Software Co-verification.**[Citation Graph (, )][DBLP]**Interactive Termination Proofs Using Termination Cores.**[Citation Graph (, )][DBLP]
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