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Daron Vroon: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Panagiotis Manolios, Daron Vroon
    Algorithms for Ordinal Arithmetic. [Citation Graph (0, 0)][DBLP]
    CADE, 2003, pp:243-257 [Conf]
  2. Panagiotis Manolios, Daron Vroon
    Termination Analysis with Calling Context Graphs. [Citation Graph (0, 0)][DBLP]
    CAV, 2006, pp:401-414 [Conf]
  3. Panagiotis Manolios, Daron Vroon
    Integrating Reasoning About Ordinal Arithmetic into ACL2. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2004, pp:82-97 [Conf]
  4. Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon
    Automatic memory reductions for RTL model verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:786-793 [Conf]
  5. Panagiotis Manolios, Daron Vroon
    Integrating static analysis and general-purpose theorem proving for termination analysis. [Citation Graph (0, 0)][DBLP]
    ICSE, 2006, pp:873-876 [Conf]
  6. John Matthews, J. Strother Moore, Sandip Ray, Daron Vroon
    Verification Condition Generation Via Theorem Proving. [Citation Graph (0, 0)][DBLP]
    LPAR, 2006, pp:362-376 [Conf]
  7. Peter C. Dillinger, Panagiotis Manolios, Daron Vroon, J. Strother Moore
    ACL2s: "The ACL2 Sedan". [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2007, v:174, n:2, pp:3-18 [Journal]
  8. Panagiotis Manolios, Daron Vroon
    Ordinal Arithmetic: Algorithms and Mechanization. [Citation Graph (0, 0)][DBLP]
    J. Autom. Reasoning, 2005, v:34, n:4, pp:387-423 [Journal]
  9. Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon
    BAT: The Bit-Level Analysis Tool. [Citation Graph (0, 0)][DBLP]
    CAV, 2007, pp:303-306 [Conf]
  10. Peter C. Dillinger, Panagiotis Manolios, Daron Vroon, J. Strother Moore
    ACL2s: "The ACL2 Sedan". [Citation Graph (0, 0)][DBLP]
    ICSE Companion, 2007, pp:59-60 [Conf]
  11. Panagiotis Manolios, Daron Vroon, Gayatri Subramanian
    Automating component-based system assembly. [Citation Graph (0, 0)][DBLP]
    ISSTA, 2007, pp:61-72 [Conf]
  12. Panagiotis Manolios, Daron Vroon
    Efficient Circuit to CNF Conversion. [Citation Graph (0, 0)][DBLP]
    SAT, 2007, pp:4-9 [Conf]

  13. Faster SAT solving with better CNF generation. [Citation Graph (, )][DBLP]


  14. Interactive Termination Proofs Using Termination Cores. [Citation Graph (, )][DBLP]


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