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Ramayya Kumar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    The FAUST - Prover. [Citation Graph (0, 0)][DBLP]
    CADE, 1992, pp:766-770 [Conf]
  2. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Automating Most Parts of Hardware Proofs in HOL. [Citation Graph (0, 0)][DBLP]
    CAV, 1991, pp:365-375 [Conf]
  3. Dirk Eisenbiegler, Ramayya Kumar
    Formally embedding existing high level synthesis algorithms. [Citation Graph (0, 0)][DBLP]
    CHARME, 1995, pp:71-83 [Conf]
  4. Thomas Kropf, Ramayya Kumar, Klaus Schneider
    Embedding Hardware Verification Within a Commercial Design Framework. [Citation Graph (0, 0)][DBLP]
    CHARME, 1993, pp:242-257 [Conf]
  5. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Hardware-Verification using First Order BDDs. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:45-62 [Conf]
  6. Klaus Schneider, Thomas Kropf, Ramayya Kumar
    Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:648-652 [Conf]
  7. Ramayya Kumar, Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid
    Formal Synthesis in Circuit Design - A Classification and Survey. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:294-309 [Conf]
  8. Sofiène Tahar, Ramayya Kumar
    Towards a Methodology for the Formal Hierarchical Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:58-62 [Conf]
  9. Thomas Kropf, Klaus Schneider, Ramayya Kumar
    A Formal Framework for High Level Synthesis. [Citation Graph (0, 0)][DBLP]
    TPCD, 1994, pp:223-238 [Conf]
  10. Dirk Eisenbiegler, Christian Blumenröhr, Ramayya Kumar
    Implementation Issues About the Embedding of Existing High Level Synthesis Algorithms in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1996, pp:157-172 [Conf]
  11. Dirk Eisenbiegler, Ramayya Kumar
    An Automata Theory Dedicated towards Formal Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1995, pp:154-169 [Conf]
  12. Dirk Eisenbiegler, Klaus Schneider, Ramayya Kumar
    A Functional Approach for Formalizing Regular Hardware Structures. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:101-114 [Conf]
  13. Ramayya Kumar, Thomas Kropf, Klaus Schneider
    Integrating a First-Order Automatic Prover in the HOL Environment. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:170-176 [Conf]
  14. Ramayya Kumar, Thomas Kropf, Klaus Schneider
    First Steps Towards Automating Hardware Proofs in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1991, pp:190-193 [Conf]
  15. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Efficient Representation and Computation of Tableau Proofs. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:39-57 [Conf]
  16. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Modelling Generic Hardware Structures by Abstract Datatypes. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1992, pp:165-175 [Conf]
  17. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:213-226 [Conf]
  18. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:385-398 [Conf]
  19. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Automating Verification by Functional Abstraction at the System Level. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1994, pp:391-406 [Conf]
  20. Sofiène Tahar, Ramayya Kumar
    Implementing a Methodology for Formally Verifying RISC Processors in HOL. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:281-294 [Conf]
  21. Sofiène Tahar, Ramayya Kumar
    Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1994, pp:424-439 [Conf]
  22. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Structurein Hardware Proofs: Fist Steps Towards Automation in a Higher-Order Environment. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:81-90 [Conf]
  23. Ramayya Kumar
    Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go? [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:- [Conf]
  24. Ramayya Kumar, Thomas Kropf, Klaus Schneider
    Formal synthesis of circuits with a simple handshake protocol. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:255-259 [Conf]
  25. Sofiène Tahar, Ramayya Kumar
    Formal Specification and Verification Techniques for RISC Pipeline Conflicts. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1995, v:38, n:2, pp:111-120 [Journal]
  26. Klaus Schneider, Ramayya Kumar, Thomas Kropf
    Accelerating Tableaux Proofs Using Compact Representations. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1994, v:5, n:1/2, pp:145-176 [Journal]
  27. Ramayya Kumar, Klaus Schneider, Thomas Kropf
    Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1993, v:2, n:2, pp:165-223 [Journal]
  28. Sofiène Tahar, Ramayya Kumar
    A Practical Methodology for the Formal Verification of RISC Processors. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1998, v:13, n:2, pp:159-225 [Journal]
  29. Thomas Wecker, Ramayya Kumar, Wolfgang Rosenstiel, Heinrich Krämer, Michael Neher
    CALLAS - ein System zur automatischen Synthese digitaler Schaltungen. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 1989, v:4, n:1, pp:37-54 [Journal]

  30. A constructive approach towards correctness of synthesis-application within retiming. [Citation Graph (, )][DBLP]


  31. Formal verification of pipeline conflicts in RISC processors. [Citation Graph (, )][DBLP]


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