SCEAS

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Ramayya Kumar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

Klaus Schneider, Ramayya Kumar, Thomas Kropf
The FAUST - Prover. [Citation Graph (0, 0)][DBLP]
CADE, 1992, pp:766-770 [Conf]
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Automating Most Parts of Hardware Proofs in HOL. [Citation Graph (0, 0)][DBLP]
CAV, 1991, pp:365-375 [Conf]
Dirk Eisenbiegler, Ramayya Kumar
Formally embedding existing high level synthesis algorithms. [Citation Graph (0, 0)][DBLP]
CHARME, 1995, pp:71-83 [Conf]
Thomas Kropf, Ramayya Kumar, Klaus Schneider
Embedding Hardware Verification Within a Commercial Design Framework. [Citation Graph (0, 0)][DBLP]
CHARME, 1993, pp:242-257 [Conf]
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Hardware-Verification using First Order BDDs. [Citation Graph (0, 0)][DBLP]
CHDL, 1993, pp:45-62 [Conf]
Klaus Schneider, Thomas Kropf, Ramayya Kumar
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. [Citation Graph (0, 0)][DBLP]
EDAC-ETC-EUROASIC, 1994, pp:648-652 [Conf]
Ramayya Kumar, Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid
Formal Synthesis in Circuit Design - A Classification and Survey. [Citation Graph (0, 0)][DBLP]
FMCAD, 1996, pp:294-309 [Conf]
Sofiène Tahar, Ramayya Kumar
Towards a Methodology for the Formal Hierarchical Verification. [Citation Graph (0, 0)][DBLP]
ICCD, 1993, pp:58-62 [Conf]
Thomas Kropf, Klaus Schneider, Ramayya Kumar
A Formal Framework for High Level Synthesis. [Citation Graph (0, 0)][DBLP]
TPCD, 1994, pp:223-238 [Conf]
Dirk Eisenbiegler, Christian Blumenröhr, Ramayya Kumar
Implementation Issues About the Embedding of Existing High Level Synthesis Algorithms in HOL. [Citation Graph (0, 0)][DBLP]
TPHOLs, 1996, pp:157-172 [Conf]
Dirk Eisenbiegler, Ramayya Kumar
An Automata Theory Dedicated towards Formal Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
TPHOLs, 1995, pp:154-169 [Conf]
Dirk Eisenbiegler, Klaus Schneider, Ramayya Kumar
A Functional Approach for Formalizing Regular Hardware Structures. [Citation Graph (0, 0)][DBLP]
HUG, 1993, pp:101-114 [Conf]
Ramayya Kumar, Thomas Kropf, Klaus Schneider
Integrating a First-Order Automatic Prover in the HOL Environment. [Citation Graph (0, 0)][DBLP]
TPHOLs, 1991, pp:170-176 [Conf]
Ramayya Kumar, Thomas Kropf, Klaus Schneider
First Steps Towards Automating Hardware Proofs in HOL. [Citation Graph (0, 0)][DBLP]
TPHOLs, 1991, pp:190-193 [Conf]
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Efficient Representation and Computation of Tableau Proofs. [Citation Graph (0, 0)][DBLP]
TPHOLs, 1992, pp:39-57 [Conf]
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Modelling Generic Hardware Structures by Abstract Datatypes. [Citation Graph (0, 0)][DBLP]
TPHOLs, 1992, pp:165-175 [Conf]
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic. [Citation Graph (0, 0)][DBLP]
HUG, 1993, pp:213-226 [Conf]
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification. [Citation Graph (0, 0)][DBLP]
HUG, 1993, pp:385-398 [Conf]
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Automating Verification by Functional Abstraction at the System Level. [Citation Graph (0, 0)][DBLP]
TPHOLs, 1994, pp:391-406 [Conf]
Sofiène Tahar, Ramayya Kumar
Implementing a Methodology for Formally Verifying RISC Processors in HOL. [Citation Graph (0, 0)][DBLP]
HUG, 1993, pp:281-294 [Conf]
Sofiène Tahar, Ramayya Kumar
Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL. [Citation Graph (0, 0)][DBLP]
TPHOLs, 1994, pp:424-439 [Conf]
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Structurein Hardware Proofs: Fist Steps Towards Automation in a Higher-Order Environment. [Citation Graph (0, 0)][DBLP]
VLSI, 1991, pp:81-90 [Conf]
Ramayya Kumar
Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go? [Citation Graph (0, 0)][DBLP]
VLSI Design, 1999, pp:- [Conf]
Ramayya Kumar, Thomas Kropf, Klaus Schneider
Formal synthesis of circuits with a simple handshake protocol. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1995, pp:255-259 [Conf]
Sofiène Tahar, Ramayya Kumar
Formal Specification and Verification Techniques for RISC Pipeline Conflicts. [Citation Graph (0, 0)][DBLP]
Comput. J., 1995, v:38, n:2, pp:111-120 [Journal]
Klaus Schneider, Ramayya Kumar, Thomas Kropf
Accelerating Tableaux Proofs Using Compact Representations. [Citation Graph (0, 0)][DBLP]
Formal Methods in System Design, 1994, v:5, n:1/2, pp:145-176 [Journal]
Ramayya Kumar, Klaus Schneider, Thomas Kropf
Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment. [Citation Graph (0, 0)][DBLP]
Formal Methods in System Design, 1993, v:2, n:2, pp:165-223 [Journal]
Sofiène Tahar, Ramayya Kumar
A Practical Methodology for the Formal Verification of RISC Processors. [Citation Graph (0, 0)][DBLP]
Formal Methods in System Design, 1998, v:13, n:2, pp:159-225 [Journal]
Thomas Wecker, Ramayya Kumar, Wolfgang Rosenstiel, Heinrich Krämer, Michael Neher
CALLAS - ein System zur automatischen Synthese digitaler Schaltungen. [Citation Graph (0, 0)][DBLP]
Inform., Forsch. Entwickl., 1989, v:4, n:1, pp:37-54 [Journal]
A constructive approach towards correctness of synthesis-application within retiming. [Citation Graph (, )][DBLP]
Formal verification of pipeline conflicts in RISC processors. [Citation Graph (, )][DBLP]

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