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Carl-Johan H. Seger: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Carl-Johan H. Seger
    Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice. [Citation Graph (0, 0)][DBLP]
    CADE, 2000, pp:235- [Conf]
  2. Randal E. Bryant, Carl-Johan H. Seger
    Formal Verification of Digital Circuits Using Symbolic Ternary System Models. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:33-43 [Conf]
  3. Scott Hazelhurst, Carl-Johan H. Seger
    Composing Symbolic Trajectory Evaluation Results. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:273-285 [Conf]
  4. John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss
    CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. [Citation Graph (0, 0)][DBLP]
    CAV, 2001, pp:131-143 [Conf]
  5. Carl-Johan H. Seger, Jeffrey J. Joyce
    A Two-Level Formal Verification Methodology using HOL and COSMOS. [Citation Graph (0, 0)][DBLP]
    CAV, 1991, pp:299-309 [Conf]
  6. Jin Yang, Carl-Johan H. Seger
    Compositional Specification and Model Checking in GSTE. [Citation Graph (0, 0)][DBLP]
    CAV, 2004, pp:216-228 [Conf]
  7. Zheng Zhu, Carl-Johan H. Seger
    The Completeness of a Hardware Inference System. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:286-298 [Conf]
  8. Mark Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger
    Formal verification of iterative algorithms in microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:201-206 [Conf]
  9. Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger
    Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:538-541 [Conf]
  10. Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger
    Parametric Representations of Boolean Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:402-407 [Conf]
  11. Randal E. Bryant, Derek L. Beatty, Carl-Johan H. Seger
    Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:397-402 [Conf]
  12. Jeffrey J. Joyce, Carl-Johan H. Seger
    Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:469-474 [Conf]
  13. Scott Hazelhurst, Carl-Johan H. Seger
    Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    Formal Hardware Verification, 1997, pp:3-78 [Conf]
  14. Robert B. Jones, Carl-Johan H. Seger, David L. Dill
    Self-Consistency Checking. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:159-171 [Conf]
  15. Mark Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger
    A Methodology for Large-Scale Hardware Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2000, pp:263-282 [Conf]
  16. Carl-Johan H. Seger
    Formal Methods in CAD from an Industrial Perspective (abstract). [Citation Graph (0, 0)][DBLP]
    FMCAD, 1998, pp:203- [Conf]
  17. Jin Yang, Carl-Johan H. Seger
    Generalized Symbolic Trajectory Evaluation - Abstraction in Action. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2002, pp:70-87 [Conf]
  18. Janusz A. Brzozowski, Carl-Johan H. Seger
    Correspondence between Ternary Simulation and Binary Race Analysis in Gate Networks (Extended Summary). [Citation Graph (0, 0)][DBLP]
    ICALP, 1986, pp:69-78 [Conf]
  19. Mark Aagaard, Carl-Johan H. Seger
    The formal verification of a pipelined double-precision IEEE floating-point multiplier. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:7-10 [Conf]
  20. Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger
    Automatic Verification of Refinement. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:225-229 [Conf]
  21. Jin Yang, Carl-Johan H. Seger
    Introduction to Generalized Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:360-367 [Conf]
  22. Carl-Johan H. Seger
    Combining functional programming and hardware verification (abstract of invited talk). [Citation Graph (0, 0)][DBLP]
    ICFP, 2000, pp:244- [Conf]
  23. Carl-Johan H. Seger, Randal E. Bryant
    Digital Circuit Verification Using Partially-Ordered State Models. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:2-7 [Conf]
  24. Carl-Johan H. Seger
    From lattices to practical formal hardware verification. [Citation Graph (0, 0)][DBLP]
    PROCOMET, 1998, pp:3-4 [Conf]
  25. Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger
    Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving. [Citation Graph (0, 0)][DBLP]
    TPHOLs, 1999, pp:323-340 [Conf]
  26. Jeffrey J. Joyce, Carl-Johan H. Seger
    The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:185-198 [Conf]
  27. Sreeranga P. Rajan, Jeffrey J. Joyce, Carl-Johan H. Seger
    From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:489-500 [Conf]
  28. Zheng Zhu, Jeffrey J. Joyce, Carl-Johan H. Seger
    Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment. [Citation Graph (0, 0)][DBLP]
    HUG, 1993, pp:253-266 [Conf]
  29. Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark Aagaard, Thomas F. Melham
    Practical Formal Verification in Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:16-25 [Journal]
  30. Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger
    Automatic Verification of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:1, pp:24-31 [Journal]
  31. Carl-Johan H. Seger, Randal E. Bryant
    Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1995, v:6, n:2, pp:147-189 [Journal]
  32. Scott Hazelhurst, Carl-Johan H. Seger
    Model Checking Lattices: Using and reasoning about information orders for abstraction. [Citation Graph (0, 0)][DBLP]
    Logic Journal of the IGPL, 1999, v:7, n:3, pp:375-411 [Journal]
  33. Carl-Johan H. Seger, Janusz A. Brzozowski
    Generalized Ternary Simulation of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITA, 1994, v:28, n:3-4, pp:159-186 [Journal]
  34. Janusz A. Brzozowski, Carl-Johan H. Seger
    A unified framework for race analysis of asynchronous networks. [Citation Graph (0, 0)][DBLP]
    J. ACM, 1989, v:36, n:1, pp:20-45 [Journal]
  35. Janusz A. Brzozowski, Carl-Johan H. Seger
    A Characterization of Ternary Simulation of Gate Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:11, pp:1318-1327 [Journal]
  36. David J. Taylor, Carl-Johan H. Seger
    Robust Storage Structures for Crash Recovery. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:4, pp:288-295 [Journal]
  37. Scott Hazelhurst, Carl-Johan H. Seger
    A simple theorem prover based on symbolic trajectory evaluation and BDD's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:413-422 [Journal]
  38. Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark Aagaard, Clark Barrett, Don Syme
    An industrially effective environment for formal hardware verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1381-1405 [Journal]
  39. Carl-Johan H. Seger
    On the Existence of Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1991, v:86, n:2, pp:343-364 [Journal]
  40. Carl-Johan H. Seger, Janusz A. Brzozowski
    An Optimistic Ternary Simulation of Gate Races. [Citation Graph (0, 0)][DBLP]
    Theor. Comput. Sci., 1988, v:61, n:, pp:49-66 [Journal]
  41. Jin Yang, Carl-Johan H. Seger
    Introduction to generalized symbolic trajectory evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:345-353 [Journal]

  42. Automatic Abstraction in Symbolic Trajectory Evaluation. [Citation Graph (, )][DBLP]


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