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Hiroyuki Watanabe: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Masaki Togai, Hiroyuki Watanabe
    A VLSI Implementation of Fuzzy Inference Engine: Toward an Expert System on a Chip. [Citation Graph (0, 0)][DBLP]
    CAIA, 1985, pp:192-197 [Conf]
  2. Hiroyuki Watanabe, Bryan D. Ackland
    Flute - a floorplanning agent for full custom VLSI design. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:601-607 [Conf]
  3. Hiroyuki Watanabe, Shinichiro Koga, Katsuhiro Kato
    Development of Learning Management System and SCO Presentation Program Based on SCORM. [Citation Graph (0, 0)][DBLP]
    ICALT, 2004, pp:- [Conf]
  4. Hironori Washizaki, Yasuhide Kobayashi, Hiroyuki Watanabe, Eiji Nakajima, Yuji Hagiwara, Kenji Hiranabe, Kazuya Fukuda
    Experiments on quality evaluation of embedded software in Japan robot software design contest. [Citation Graph (0, 0)][DBLP]
    ICSE, 2006, pp:551-560 [Conf]
  5. Hiroyuki Watanabe, James R. Symon, Wayne D. Dettloff, Kathy E. Yount
    VLSI Fuzzy Chip and Inference Accelerator Board Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:120-127 [Conf]
  6. Hiroyuki Watanabe
    Heuristic Graph Displayer for G-BASE. [Citation Graph (0, 0)][DBLP]
    International Journal of Man-Machine Studies, 1989, v:30, n:3, pp:287-302 [Journal]
  7. Masaki Togai, Hiroyuki Watanabe
    A VLSI implementation of a fuzzy-inference engine: Toward an expert system on a chip. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1986, v:38, n:2, pp:147-163 [Journal]
  8. Gershon Kedem, Hiroyuki Watanabe
    Graph-Optimization Techniques for IC Layout and Compaction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:1, pp:12-20 [Journal]
  9. Hironori Washizaki, Rieko Namiki, Tomoyuki Fukuoka, Yoko Harada, Hiroyuki Watanabe
    A Framework for Measuring and Evaluating Program Source Code Quality. [Citation Graph (0, 0)][DBLP]
    PROFES, 2007, pp:284-299 [Conf]

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