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Parimal Patel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bala Krishnan D. Achie, Ajaykrishna Sreehari, Parimal Patel
    FPGA Based Implementation of MD5 Message-Digest Algorithm for IPSEC Authentication. [Citation Graph (0, 0)][DBLP]
    CAINE, 2005, pp:372-375 [Conf]
  2. Apurva Mistry, Parimal Patel
    Prototyped Embedded Application for IGMP Version 2 Protocol. [Citation Graph (0, 0)][DBLP]
    CAINE, 2004, pp:138-142 [Conf]
  3. Sumit N. Vora, Parimal Patel
    Architecture for Context-driven Packet Payload Processing Engine. [Citation Graph (0, 0)][DBLP]
    CAINE, 2004, pp:115-119 [Conf]
  4. Chirag Parikh, Parimal Patel
    Design and Implementation of AES (Rijndael) Algorithm. [Citation Graph (0, 0)][DBLP]
    CAINE, 2004, pp:85-89 [Conf]
  5. Parimal Patel, Chirag Parikh
    Design and Implementation of AES (Rijndael) Algorithm. [Citation Graph (0, 0)][DBLP]
    CAINE, 2003, pp:126-130 [Conf]
  6. Parimal Patel, Ashok Kumar Tummala, Hari Babu Ramineni, Wei-Ming Lin
    Improved Design and Implementation of Network Intrusion Detection System for Gigabit Network Traffic Using FPGA. [Citation Graph (0, 0)][DBLP]
    CAINE, 2005, pp:382-386 [Conf]
  7. Narayanam Ranganadh, Parimal Patel, Artyom M. Grigoryan
    Implementation of the DFT Using Radix-2 and Paired Transform Algorithms. [Citation Graph (0, 0)][DBLP]
    CAINE, 2004, pp:148-153 [Conf]
  8. Venkataramana Reddipalli, Sri Pallavi Padala, Parimal Patel
    Design and Implementation of ATM NIC in FPGA. [Citation Graph (0, 0)][DBLP]
    CAINE, 2002, pp:193-196 [Conf]
  9. Parimal Patel, Chirag Parikh
    An Efficient Design and Implementation of DES and Triple-DES Algorithms. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2003, pp:40-43 [Conf]
  10. Parimal Patel, Venkataramana Reddipalli
    Design Considerations of Implementing a Superscalar CPU in FPGA. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2003, pp:296-299 [Conf]
  11. Wei-Ming Lin, Ramu Madhavaram, Parimal Patel, Fred Hudson
    A Real-Time Ad Hoc Packet Matching Technique for Hardware-Based Network Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2004, pp:382-0 [Conf]
  12. Parimal Patel, Venkataramana Reddipalli
    Implementation of write relocatable coherency protocol in multiple processor architectures. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2001, pp:511-516 [Conf]
  13. Parimal Patel, Harish Maiya
    Implementation comparison of multicasting policies in an ATM switch. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2001, pp:505-510 [Conf]
  14. Parimal Patel, Saad Zahid
    Design Considerations in an ATM Switch Design. [Citation Graph (0, 0)][DBLP]
    ICCCN, 1998, pp:92-98 [Conf]
  15. Parimal Patel
    Embedded Systems Design Using FPGA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:20- [Conf]
  16. Parimal Patel
    Tutorial IND2A: Embedded Systems Design with Xilinx Virtex-5 Series FPGA. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:16- [Conf]
  17. Devang Pandya, Christopher J. Martinez, Wei-Ming Lin, Parimal Patel
    Advanced hashing techniques for non-uniformly distributed IP address lookup. [Citation Graph (0, 0)][DBLP]
    Communications and Computer Networks, 2006, pp:46-51 [Conf]
  18. Christopher J. Martinez, Wei-Ming Lin, Parimal Patel
    Optimal XOR hashing for a linearly distributed address lookup in computer networks. [Citation Graph (0, 0)][DBLP]
    ANCS, 2005, pp:203-210 [Conf]
  19. Parimal Patel, Chung Chang
    Performance improvement using fill unit. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 1999, pp:254-259 [Conf]
  20. Parimal Patel, Chirag Parikh
    Low Power Implementation of AES (RIJNDAEL) Algorithm. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2007, pp:7-11 [Conf]
  21. Parimal Patel, Ashok Kumar Tummala
    Detecting TCP Port Scans Generated by NMAP using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2007, pp:266-270 [Conf]
  22. Ashok Kumar Tummala, Parimal Patel
    Distributed IDS using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  23. Christopher J. Martinez, Wei-Ming Lin, Parimal Patel
    Optimal XOR hashing for non-uniformly distributed address lookup in computer networks. [Citation Graph (0, 0)][DBLP]
    J. Network and Computer Applications, 2007, v:30, n:4, pp:1397-1427 [Journal]

  24. Selection and Implementation of an EAP Authentication Protocol for Hand-held Devices. [Citation Graph (, )][DBLP]


  25. The Design of Efficient Hashing Techniques for IP Address Lookup. [Citation Graph (, )][DBLP]


  26. Implementation of an IEEE 802.11i based Wireless Security System. [Citation Graph (, )][DBLP]


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