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Behnam S. Arad: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Behnam S. Arad, Ashwin K. Sutrave
    An Efficient Arithmetic Unit Based on Residue Number System. [Citation Graph (0, 0)][DBLP]
    CAINE, 2002, pp:1-4 [Conf]
  2. Ashraf El-Nakhal, Behnam S. Arad
    PCI-EXPRESS Transaction Layer and Application Layer of A 3-Port Switch. [Citation Graph (0, 0)][DBLP]
    CAINE, 2005, pp:274-279 [Conf]
  3. Chia-Hung Kuo, Behnam S. Arad
    Design and Simulation of a Pipelined Microprocessor. [Citation Graph (0, 0)][DBLP]
    CAINE, 2001, pp:5-8 [Conf]
  4. Behnam S. Arad, Sachin Rudrapatna
    A 32-bit Residue Arithmetic Unit for High Performance Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2005, pp:320-325 [Conf]
  5. Chung-Seok (Andy) Seo, Abhijit Chatterjee, Timothy J. Drabik, Behnam S. Arad, Reena Patel
    Prototyping an Embedded Bus-Based Parallel System. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2005, pp:314-319 [Conf]
  6. Behnam S. Arad, Chien-Hsun Wang
    Design of a processing element for bus-based parallel computing. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2000, pp:228-231 [Conf]
  7. Behnam S. Arad, Hung-Ru Shih
    A pipelined processor suitable for a bus-based parallel architecture. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2001, pp:485-488 [Conf]
  8. Behnam S. Arad, Ahmed El-Amawy
    On Fault Tolerant Training of Feedforward Neural Networks. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 1997, v:10, n:3, pp:539-553 [Journal]
  9. Behnam S. Arad, Ahmed El-Amawy
    Mapping a class of neural networks on k-ary n-cubes. [Citation Graph (0, 0)][DBLP]
    Telecommunication Systems, 1998, v:10, n:1, pp:67-78 [Journal]
  10. Mohamed Mahmoud, Behnam S. Arad
    Modeling and Verification of the Physical Layer of PCI Express. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2007, pp:289-294 [Conf]

  11. A Behavioral Simulator for PCI-Express Transaction Layer. [Citation Graph (, )][DBLP]

  12. A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog. [Citation Graph (, )][DBLP]

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