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Daniel A. Jiménez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ravi V. Batchu, Daniel A. Jiménez
    Exploiting Procedure Level Locality to Reduce Instruction Cache Misses. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:75-84 [Conf]
  2. Daniel A. Jiménez, Heather L. Hanson, Calvin Lin
    Boolean Formula-Based Branch Prediction for Future Technologies. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:97-106 [Conf]
  3. Daniel A. Jiménez
    Reconsidering Complex Branch Predictors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:43-52 [Conf]
  4. Daniel A. Jiménez, Calvin Lin
    Dynamic Branch Prediction with Perceptrons. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:197-206 [Conf]
  5. Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
    Toward an Evaluation Infrastructure for Power and Energy Optimizations. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  6. Daniel A. Jiménez
    Piecewise Linear Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:382-393 [Conf]
  7. Daniel A. Jiménez
    Fast Path-Based Neural Branch Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:243-252 [Conf]
  8. Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin
    The impact of delay on the design of branch predictors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:67-76 [Conf]
  9. Daniel A. Jiménez
    Code placement for improving dynamic branch prediction accuracy. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:107-116 [Conf]
  10. Daniel A. Jiménez
    Improved latency and accuracy for neural branch prediction. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2005, v:23, n:2, pp:197-218 [Journal]
  11. Daniel A. Jiménez, Calvin Lin
    Neural methods for dynamic branch prediction. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2002, v:20, n:4, pp:369-397 [Journal]
  12. Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
    Efficient Program Power Behavior Characterization. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:183-197 [Conf]

  13. A Flexible Heterogeneous Multi-Core Architecture. [Citation Graph (, )][DBLP]


  14. A decoupled KILO-instruction processor. [Citation Graph (, )][DBLP]


  15. A Two-Level Load/Store Queue Based on Execution Locality. [Citation Graph (, )][DBLP]


  16. Low-power, high-performance analog neural branch prediction. [Citation Graph (, )][DBLP]


  17. Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors. [Citation Graph (, )][DBLP]


  18. Chained In-Order/Out-of-Order DoubleCore Architecture. [Citation Graph (, )][DBLP]


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