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R. Iris Bahar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Eric Chi, A. Michael Salem, R. Iris Bahar, Richard S. Weiss
    Combining Software and Hardware Monitoring for Improved Power and Performance Tuning. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2003, pp:57-64 [Conf]
  2. Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino
    Computing the Maximum Power Cycles of a Sequential Circuit. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:23-28 [Conf]
  3. Tali Moreshet, R. Iris Bahar
    Power-aware issue queue design for speculative instructions. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:634-637 [Conf]
  4. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Designing logic circuits for probabilistic computation in the presence of noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:485-490 [Conf]
  5. Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss
    A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:705-708 [Conf]
  6. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Designing MRF based error correcting circuits for memory elements. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:792-793 [Conf]
  7. R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
    Timing Analysis of Combinational Circuits using ADD's. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:625-629 [Conf]
  8. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Optimizing noise-immune nanoscale circuits using principles of Markov random fields. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:149-152 [Conf]
  9. Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
    RESTA: a robust and extendable symbolic timing analysis tool. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:407-412 [Conf]
  10. R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Algebraic decision diagrams and their applications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:188-191 [Conf]
  11. R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
    A symbolic method to reduce power consumption of circuits containing false paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:368-371 [Conf]
  12. R. Iris Bahar, Joseph L. Mundy, Jie Chen
    A Probabilistic-Based Design Methodology for Nanoscale Computation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:480-486 [Conf]
  13. R. Iris Bahar, Fabio Somenzi
    Boolean techniques for low power driven re-synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:428-432 [Conf]
  14. Yu Bai, R. Iris Bahar
    Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:54-57 [Conf]
  15. Brian R. Fisk, R. Iris Bahar
    The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:538-545 [Conf]
  16. Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss
    Fetch Halting on Critical Load Misses. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:244-249 [Conf]
  17. Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein
    Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:70-75 [Conf]
  18. R. Iris Bahar, Srilatha Manne
    Power and energy reduction via pipeline balancing. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:218-229 [Conf]
  19. R. Iris Bahar, Gianluca Albera, Srilatha Manne
    Power and performance tradeoffs using various caching strategies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:64-69 [Conf]
  20. R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi
    Symbolic computation of logic implications for technology-dependent low-power synthesis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:163-168 [Conf]
  21. Tali Moreshet, R. Iris Bahar, Maurice Herlihy
    Energy reduction in multiprocessor systems using transactional memory. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:331-334 [Conf]
  22. Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi
    CMOS dynamic power estimation based on collapsible current source transistor modeling. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:111-116 [Conf]
  23. Yu Bai, R. Iris Bahar
    A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:139-148 [Conf]
  24. Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
    Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:203-208 [Conf]
  25. Roberto Maro, Yu Bai, R. Iris Bahar
    Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:97-111 [Conf]
  26. Tali Moreshet, R. Iris Bahar, Maurice Herlihy
    Energy implications of multiprocessor synchronization. [Citation Graph (0, 0)][DBLP]
    SPAA, 2006, pp:329- [Conf]
  27. R. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi
    Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:295-297 [Journal]
  28. R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
    Algebraic Decision Diagrams and Their Applications. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1997, v:10, n:2/3, pp:171-206 [Journal]
  29. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:5, pp:19-27 [Journal]
  30. Yu Bai, R. Iris Bahar
    A low-power in-order/out-of-order issue queue. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:2, pp:152-179 [Journal]
  31. R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
    Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1101-1115 [Journal]
  32. R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein
    Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:502-515 [Journal]
  33. Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein
    Timing analysis for full-custom circuits using symbolic DC formulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1815-1830 [Journal]
  34. R. Iris Bahar, Ernest T. Lampe, Enrico Macii
    Power optimization of technology-dependent circuits based on symbolic computation of logic implications. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:267-293 [Journal]
  35. Tali Moreshet, R. Iris Bahar
    Effects of speculation on performance and issue queue design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1123-1126 [Journal]
  36. D. Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein
    Accurate timing analysis using SAT and pattern-dependent delay models. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1018-1023 [Conf]
  37. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:576-581 [Conf]
  38. Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
    Designing Nanoscale Logic Circuits Based on Markov Random Fields. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:2-3, pp:255-266 [Journal]

  39. Detecting errors using multi-cycle invariance information. [Citation Graph (, )][DBLP]


  40. High-performance, cost-effective heterogeneous 3D FPGA architectures. [Citation Graph (, )][DBLP]


  41. Temperature-insensitive synthesis using multi-vt libraries. [Citation Graph (, )][DBLP]


  42. Energy efficient synchronization techniques for embedded architectures. [Citation Graph (, )][DBLP]


  43. Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. [Citation Graph (, )][DBLP]


  44. High-performance, cost-effective heterogeneous 3D FPGA architectures. [Citation Graph (, )][DBLP]


  45. Energy-optimal synchronization primitives for single-chip multi-processors. [Citation Graph (, )][DBLP]


  46. Improving the testability and reliability of sequential circuits with invariant logic. [Citation Graph (, )][DBLP]


  47. Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. [Citation Graph (, )][DBLP]


  48. Strategies for improving the parametric yield and profits of 3D ICs. [Citation Graph (, )][DBLP]


  49. Compacting test vector sets via strategic use of implications. [Citation Graph (, )][DBLP]


  50. Trends and Future Directions in Nano Structure Based Computing and Fabrication. [Citation Graph (, )][DBLP]


  51. Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. [Citation Graph (, )][DBLP]


  52. Reducing the leakage and timing variability of 2D ICcs using 3D ICs. [Citation Graph (, )][DBLP]


  53. Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. [Citation Graph (, )][DBLP]


  54. Architectures for Silicon Nanoelectronics and Beyond. [Citation Graph (, )][DBLP]


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