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Hiroshi Nakamura: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura
    Data Movement Optimization for Software-Controlled On-Chip Memory. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:120-127 [Conf]
  2. Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno
    Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:162-172 [Conf]
  3. Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
    Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:184-195 [Conf]
  4. Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka
    A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. [Citation Graph (0, 0)][DBLP]
    CAV, 1990, pp:76-85 [Conf]
  5. Ken-ichi Kurata, Vincent Breton, Hiroshi Nakamura
    A Method to Find Uniq e Sequences on Distrib ted Genomic Databases. [Citation Graph (0, 0)][DBLP]
    CCGRID, 2003, pp:62-69 [Conf]
  6. Ken-ichi Kurata, Hiroshi Nakamura, Vincent Breton
    Secret sequence comparison on public grid computing resources. [Citation Graph (0, 0)][DBLP]
    CCGRID, 2005, pp:832-839 [Conf]
  7. Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura
    An intra-task dvfs technique based on statistical analysis of hardware events. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:123-130 [Conf]
  8. Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya
    Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10276-10281 [Conf]
  9. Hiroshi Nakamura, Kisaburo Nakazawa, Hang Li, Hiromitsu Imori, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita
    Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:368-377 [Conf]
  10. Masaaki Kondo, Hiroshi Nakamura
    A Small, Fast and Low-Power Register File by Bit-Partitioning. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:40-49 [Conf]
  11. Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku
    SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:105-0 [Conf]
  12. Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
    A Data Alignment Technique for Improving Cache Performance. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:587-592 [Conf]
  13. Taisuke Boku, Ken'ichi Itakura, Hiroshi Nakamura, Kisaburo Nakazawa
    CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:108-115 [Conf]
  14. Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita
    A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:298-307 [Conf]
  15. Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku
    Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. [Citation Graph (0, 0)][DBLP]
    Intelligent Memory Systems, 2000, pp:15-32 [Conf]
  16. Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, Yoshihiko Hotta
    MegaProto: A Low-Power and Compact Cluster for High-Performance Computing. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  17. Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, Hiroshi Nakashima, Hiroshi Nakamura, Satoshi Matsuoka, Yoshihiko Hotta
    MegaProto/E: power-aware high-performance cluster with commodity technology. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  18. Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
    Improving cache Performance Through Tiling and Data Alignment. [Citation Graph (0, 0)][DBLP]
    IRREGULAR, 1997, pp:167-185 [Conf]
  19. Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya
    Control signal sharing of asynchronous circuits using datapath delay information. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:617-620 [Conf]
  20. Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya
    A zero-time-overhead asynchronous four-phase controller. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:205-208 [Conf]
  21. Masaaki Kondo, Mitsugu Iwamoto, Hiroshi Nakamura
    Cache Line Impact on 3D PDE Solvers. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:301-309 [Conf]
  22. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
    Energy-efficient dynamic instruction scheduling logic through instruction grouping. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:43-48 [Conf]
  23. Masahiro Fujita, Hiroshi Nakamura
    The standard SpecC language. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:81-86 [Conf]
  24. Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya
    Logic Optimization for Asynchronous SI Controllers using Transduction Method. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:245-250 [Conf]
  25. Kohji Itoh, Hiroshi Nakamura, Shunsuke Unno, Jun'ichi Kakegawa
    A System Assisting Acquisition of Japanese Expressions Through Read-Write-Hear-Speaking and Comparing Between Use Cases of Relevant Expressions. [Citation Graph (0, 0)][DBLP]
    KES (2), 2006, pp:1071-1078 [Conf]
  26. Masahiro Fujita, Makoto Ishisone, Hiroshi Nakamura, Hidehiko Tanaka, Tohru Moto-Oka
    Using the Temporal Logic Programming Language Tokio for Algorithm Description and Automatic CMOS Gate Array Synthesis. [Citation Graph (0, 0)][DBLP]
    LP, 1985, pp:246-255 [Conf]
  27. Hiroshi Nakamura, Masaya Nakai, Shinji Kono, Masahiro Fujita, Hidehiko Tanaka
    Logic Design Assistence Using Temporal Logic Based Language Tokio. [Citation Graph (0, 0)][DBLP]
    LP, 1989, pp:174-183 [Conf]
  28. Masaaki Kondo, Hiroshi Nakamura
    Dynamic Processor Throttling for Power Efficient Computations. [Citation Graph (0, 0)][DBLP]
    PACS, 2004, pp:120-134 [Conf]
  29. Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura
    Dynamic Instruction Cascading on GALS Microprocessors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:30-39 [Conf]
  30. Ken-ichi Kurata, Christian Saguez, Gerald Dine, Hiroshi Nakamura
    Rapid Analysis of Specificity of PCR Product on the Whole Genome. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:246-252 [Conf]
  31. Hiroshi Nakamura, Takanori Arai, Masahiro Fujita
    Formal Verification of a Pipelined Processor with New Memory. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:321-324 [Conf]
  32. Daisuke Komura, Hiroshi Nakamura, Shuichi Tsutsumi, Hiroyuki Aburatani, Sigeo Ihara
    Multidimensional support vector machines for visualization of gene expression data. [Citation Graph (0, 0)][DBLP]
    SAC, 2004, pp:175-179 [Conf]
  33. Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, Yoshihiko Hotta
    MegaProto: 1 TFlops/10kW Rack Is Feasible Even with Only Commodity Technology. [Citation Graph (0, 0)][DBLP]
    SC, 2005, pp:28- [Conf]
  34. Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori, Shun Kawabe
    Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:642-651 [Conf]
  35. Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
    Skewed Checkpointing for Tolerating Multi-Node Failures. [Citation Graph (0, 0)][DBLP]
    SRDS, 2004, pp:116-125 [Conf]
  36. Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato
    SCIMA-SMP: on-chip memory processor architecture for SMP. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:121-128 [Conf]
  37. Daisuke Komura, Hiroshi Nakamura, Shuichi Tsutsumi, Hiroyuki Aburatani, Sigeo Ihara
    Multidimensional support vector machines for visualization of gene expression data. [Citation Graph (0, 0)][DBLP]
    Bioinformatics, 2005, v:21, n:4, pp:439-444 [Journal]
  38. S. Aoki, R. Burkhalter, K. Kanaya, T. Yoshié, Taisuke Boku, Hiroshi Nakamura, Yoshiyuki Yamashita
    Performance of lattice QCD programs on CP-PACS. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1999, v:25, n:10-11, pp:1243-1255 [Journal]
  39. Nicolas Jacq, Christophe Blanchet, Christophe Combet, E. Cornillot, Laurent Duret, Ken-ichi Kurata, Hiroshi Nakamura, T. Silvestre, Vincent Breton
    Grid as a bioinformatic tool. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2004, v:30, n:9-10, pp:1093-1107 [Journal]
  40. Kisaburo Nakazawa, Hiroshi Nakamura, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita
    CP-PACS: A massively parallel processor at the University of Tsukuba. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1999, v:25, n:13-14, pp:1635-1661 [Journal]
  41. Masaaki Kondo, Motonobu Fujita, Hiroshi Nakamura
    Software-controlled on-chip memory for high-performance and low-power computing. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2002, v:30, n:3, pp:7-8 [Journal]
  42. Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau
    Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:142-149 [Journal]
  43. Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
    Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:797-802 [Conf]
  44. Hiroshi Nakamura
    Fast Abstracts. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:812- [Conf]
  45. Masaaki Kondo, Yoshimichi Ikeda, Hiroshi Nakamura
    A High Performance Cluster System Design by Adaptie Power Control. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]

  46. Power reduction of chip multi-processors using shared resource control cooperating with DVFS. [Citation Graph (, )][DBLP]


  47. A fine-grain dynamic sleep control scheme in MIPS R3000. [Citation Graph (, )][DBLP]


  48. Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values. [Citation Graph (, )][DBLP]


  49. Cooperative shared resource access control for low-power chip multiprocessors. [Citation Graph (, )][DBLP]


  50. Adaptive power gating for function units in a microprocessor. [Citation Graph (, )][DBLP]


  51. A Proposal of New Dependable Database Middleware with Consistency and Concurrency Control. [Citation Graph (, )][DBLP]


  52. Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies. [Citation Graph (, )][DBLP]


  53. Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. [Citation Graph (, )][DBLP]


  54. Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. [Citation Graph (, )][DBLP]


  55. Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. [Citation Graph (, )][DBLP]


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