Search the dblp DataBase

Publications of Author

1. Wei-Chung Hsu, Howard Chen, Pen-Chung Yew, Dong-yuan Chen
   On the Predictability of Program Behavior Using Different Input Data Sets. [Citation Graph (0, 0)][DBLP]
   Interaction between Compilers and Computer Architectures, 2002, pp:45-0 [Conf]
   
2. Dong-yuan Chen, Lixia Liu, Chen Fu, Shuxin Yang, Chengyong Wu, Roy Dz-Ching Ju
   Efficient Resource Management during Instruction Scheduling for the EPIC Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2003, pp:36-45 [Conf]
   
3. Howard Chen, Wei-Chung Hsu, Dong-yuan Chen
   Dynamic Trace Selection Using Performance Monitoring Hardware Sampling. [Citation Graph (0, 0)][DBLP]
   CGO, 2003, pp:79-90 [Conf]
   
4. Abhinav Das, Jiwei Lu, Howard Chen, Jinpyo Kim, Pen-Chung Yew, Wei-Chung Hsu, Dong-yuan Chen
   Performance of Runtime Optimization on BLAST. [Citation Graph (0, 0)][DBLP]
   CGO, 2005, pp:86-96 [Conf]
   
5. Youfeng Wu, Dong-yuan Chen, Jesse Fang
   Better exploration of region-level value locality with integrated computation reuse and value prediction. [Citation Graph (0, 0)][DBLP]
   ISCA, 2001, pp:98-108 [Conf]
   
6. Pohua P. Chang, Dong-yuan Chen, Yong-Fong Lee, Youfeng Wu, Utpal Banerjee
   Bidirectional Scheduling: A New Global Code Scheduling Approach. [Citation Graph (0, 0)][DBLP]
   LCPC, 1996, pp:222-230 [Conf]
   
7. Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung Yew, Dong-yuan Chen
   The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System. [Citation Graph (0, 0)][DBLP]
   MICRO, 2003, pp:180-190 [Conf]
   
8. Dong-yuan Chen, Lixia Liu, Roy Dz-Ching Ju, Chen Fu, Shuxin Yang, Chengyong Wu
   Efficient Modeling of Itanium Architecture during Instruction Scheduling using Extended Finite State Automata. [Citation Graph (0, 0)][DBLP]
   J. Instruction-Level Parallelism, 2004, v:6, n:, pp:- [Journal]
   
9. 
   Practical experiences with Java software transactional memory. [Citation Graph (, )][DBLP]