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Jean Jyh-Jiun Shann:
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Publications of Author
- Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung
Code Compression by Register Operand Dependency. [Citation Graph (0, 0)][DBLP] Interaction between Compilers and Computer Architectures, 2002, pp:91-101 [Conf]
- Kuen-Cheng Chiang, Zhi-Wei Chen, Jean Jyh-Jiun Shann
Design and implementation of a reconfigurable hardware for secure embedded systems. [Citation Graph (0, 0)][DBLP] ASIACCS, 2006, pp:364- [Conf]
- Wei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu
Low-Power Data Address Bus Encoding Method. [Citation Graph (0, 0)][DBLP] CDES, 2005, pp:204-210 [Conf]
- Yau-Chong Hu, Wei-Hau Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, Wen-Feng Chen
Low-Power Branch Prediction. [Citation Graph (0, 0)][DBLP] CDES, 2005, pp:211-217 [Conf]
- S.-K. Cheng, R.-Ming Shiu, Jean Jyh-Jiun Shann
Decoding Unit with High Issue Rate for X86 Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP] ICPADS, 1998, pp:488-495 [Conf]
- Hui-Yue Hwang, R.-Ming Shiu, Jean Jyh-Jiun Shann
An X86 Load/Store Unit with Aggressive Scheduling of Load/Store Operations. [Citation Graph (0, 0)][DBLP] ICPADS, 1998, pp:496-503 [Conf]
- Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung
A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems. [Citation Graph (0, 0)][DBLP] ITCC (2), 2004, pp:229-235 [Conf]
- Hsin-Chia Fu, Jean Jyh-Jiun Shann
A Fuzzy Neural Network for Knowledge Learning. [Citation Graph (0, 0)][DBLP] Int. J. Neural Syst., 1994, v:5, n:1, pp:13-22 [Journal]
- Cher-Sheng Cheng, Chung-Ping Chung, Jean Jyh-Jiun Shann
Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems. [Citation Graph (0, 0)][DBLP] Inf. Process. Manage., 2006, v:42, n:3, pp:729-750 [Journal]
- Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung
Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems. [Citation Graph (0, 0)][DBLP] Inf. Process. Manage., 2006, v:42, n:2, pp:407-428 [Journal]
- Wann-Yun Shieh, Tien-Fu Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung
Inverted file compression through document identifier reassignment. [Citation Graph (0, 0)][DBLP] Inf. Process. Manage., 2003, v:39, n:1, pp:117-131 [Journal]
- Wann-Yun Shieh, Jean Jyh-Jiun Shann, Chung-Ping Chung
An Inverted File Cache for Fast Information Retrieval. [Citation Graph (0, 0)][DBLP] J. Inf. Sci. Eng., 2003, v:19, n:4, pp:681-695 [Journal]
- R.-Ming Shiu, Hui-Yue Hwang, Jean Jyh-Jiun Shann
Aggressive Schduling for Memory Accesses of CISC Superscalar Microprocessors. [Citation Graph (0, 0)][DBLP] J. Inf. Sci. Eng., 2001, v:17, n:5, pp:787-803 [Journal]
- Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung
Code compression by register operand dependency. [Citation Graph (0, 0)][DBLP] Journal of Systems and Software, 2004, v:72, n:3, pp:295-304 [Journal]
- Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung
A software/hardware cooperated stack operations folding model for Java processors. [Citation Graph (0, 0)][DBLP] Journal of Systems and Software, 2004, v:72, n:3, pp:377-387 [Journal]
- Kelvin Lin, Chung-Ping Chung, Jean Jyh-Jiun Shann
Compressing MIPS code by multiple operand dependencies. [Citation Graph (0, 0)][DBLP] ACM Trans. Embedded Comput. Syst., 2003, v:2, n:4, pp:482-508 [Journal]
- Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung
Design of an optimal folding mechanism for Java processors. [Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2002, v:26, n:8, pp:341-352 [Journal]
- I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann
Instruction Set Extension Generation with Considering Physical Constraints. [Citation Graph (0, 0)][DBLP] HiPEAC, 2007, pp:291-305 [Conf]
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor. [Citation Graph (, )][DBLP]
Instruction Set Extension Exploration in Multiple-Issue Architecture. [Citation Graph (, )][DBLP]
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. [Citation Graph (, )][DBLP]
Methods for Precise False-Overlap Detection in Tile-Based Rendering. [Citation Graph (, )][DBLP]
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