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Chung-Ping Chung: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung
    Code Compression by Register Operand Dependency. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2002, pp:91-101 [Conf]
  2. Wei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu
    Low-Power Data Address Bus Encoding Method. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:204-210 [Conf]
  3. Yau-Chong Hu, Wei-Hau Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, Wen-Feng Chen
    Low-Power Branch Prediction. [Citation Graph (0, 0)][DBLP]
    CDES, 2005, pp:211-217 [Conf]
  4. Bin-Hua Tein, I-Wei Wu, Chung-Ping Chung
    Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:91-96 [Conf]
  5. Hui-Chin Yang, Chung-Ping Chung
    Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability. [Citation Graph (0, 0)][DBLP]
    CDES, 2006, pp:146-152 [Conf]
  6. Lee-Ren Ton, Lung-Chung Chang, Chung-Ping Chung
    Exploiting Java Bytecode Parallelism by Enhanced POC Folding Model (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:994-997 [Conf]
  7. Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung
    Design of Instruction Stream Buffer with Trace Support for X86 Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:294-299 [Conf]
  8. Shyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung
    Instruction Cache Prefetching with Extended BTB. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:360-0 [Conf]
  9. Ruey-Liang Ma, Chung-Ping Chung
    Branch Prediction for Enhancing Fine-Grained Parallelism in Prolog. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:744-751 [Conf]
  10. Chang-Chung Liu, R.-Ming Shiu, Chung-Ping Chung
    Register renaming for x86 superscalar design. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1996, pp:336-343 [Conf]
  11. Lee-Ren Ton, Lung-Chung Chang, Min-Fu Kao, Han-Min Tseng, Shi-Sheng Shang, Ruey-Liang Ma, Dze-Chaung Wang, Chung-Ping Chung
    Instruction Folding in Java Processor. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1997, pp:138-143 [Conf]
  12. Wann-Yun Shieh, Chung-Ping Chung
    A Statistics-Based Approach to Incrementally Update Inverted Files. [Citation Graph (0, 0)][DBLP]
    IKE, 2003, pp:38-43 [Conf]
  13. Wann-Yun Shieh, Tien-Fu Chen, Chung-Ping Chung
    A Tree-Based inverted File for Fast Ranked-Document Retrieval. [Citation Graph (0, 0)][DBLP]
    IKE, 2003, pp:64-69 [Conf]
  14. Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung
    A Unique-Order Interpolative Code for Fast Querying and Space-Efficient Indexing in Information Retrieval Systems. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:229-235 [Conf]
  15. Hong Chich Chou, Chung-Ping Chung
    Modeling of Superscalar Instruction Scheduling and Analysis of a Heuristic Scheduling Algorithm. [Citation Graph (0, 0)][DBLP]
    BIT, 1993, v:33, n:3, pp:354-371 [Journal]
  16. Ruey-Liang Ma, Chung-Ping Chung
    Periodic Adaptive Branch Prediction and its Application in Superscalar Processing in Prolog. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1995, v:38, n:6, pp:457-470 [Journal]
  17. Hong Chich Chou, Chung-Ping Chung
    Optimal multiprocessor task scheduling using dominance and equivalence relations. [Citation Graph (0, 0)][DBLP]
    Computers & OR, 1994, v:21, n:4, pp:463-475 [Journal]
  18. Cher-Sheng Cheng, Chung-Ping Chung, Jean Jyh-Jiun Shann
    Fast query evaluation through document identifier assignment for inverted file-based information retrieval systems. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Manage., 2006, v:42, n:3, pp:729-750 [Journal]
  19. Cher-Sheng Cheng, Jean Jyh-Jiun Shann, Chung-Ping Chung
    Unique-order interpolative coding for fast querying and space-efficient indexing in information retrieval systems. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Manage., 2006, v:42, n:2, pp:407-428 [Journal]
  20. Wann-Yun Shieh, Chung-Ping Chung
    A statistics-based approach to incrementally update inverted files. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Manage., 2005, v:41, n:2, pp:275-288 [Journal]
  21. Wann-Yun Shieh, Tien-Fu Chen, Jean Jyh-Jiun Shann, Chung-Ping Chung
    Inverted file compression through document identifier reassignment. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Manage., 2003, v:39, n:1, pp:117-131 [Journal]
  22. Cheng Chen, Chung-Ping Chung, Cheng-Chin Chiang, Hsin-Chia Fu, S. J. Wang
    An Or-Parallel Inference Model Based on Multi RISC-Style Processing System. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1991, v:7, n:4, pp:487-512 [Journal]
  23. Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung
    Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2002, v:18, n:3, pp:393-409 [Journal]
  24. Jih-Ching Chiu, Michael Jin-Yi Wang, Chung-Ping Chung
    Design of Instruction Address Queue for High Degree X86 Superscalar Architecture. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2002, v:18, n:3, pp:393-409 [Journal]
  25. Chung-Ping Chung, Shyi-Chyi Jeng, Hong Chich Chou, Cheng Chen
    Design of Dual-ALU CRISC and Its Concurrent Execution . [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1989, v:5, n:3, pp:251-274 [Journal]
  26. Wann-Yun Shieh, Jean Jyh-Jiun Shann, Chung-Ping Chung
    An Inverted File Cache for Fast Information Retrieval. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2003, v:19, n:4, pp:681-695 [Journal]
  27. Ruey-Liang Ma, Chung-Ping Chung
    Reducing Memory Traffic and Accelerting Prolog Execution in a Superscalar Prolog System. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1999, v:15, n:6, pp:859-884 [Journal]
  28. Neng-Pin Lu, Chung-Ping Chung
    A Fault-Tolerant Multistage Combining Network. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1996, v:34, n:1, pp:14-28 [Journal]
  29. Yung-Cheng Ma, Tien-Fu Chen, Chung-Ping Chung
    Branch-and-bound task allocation with task clustering-based pruning. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2004, v:64, n:11, pp:1223-1240 [Journal]
  30. Lee-Ren Ton, Lung-Chung Chang, Chung-Ping Chung
    An analytical POC stack operations folding for continuous and discontinuous Java bytecodes. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:1-3, pp:1-16 [Journal]
  31. Ching-Wen Chen, Chung-Ping Chung
    Fault-tolerant gamma interconnection network without backtracking. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2001, v:58, n:1, pp:23-31 [Journal]
  32. Ching-Wen Chen, Neng-Pin Lu, Chung-Ping Chung
    3-Disjoint gamma interconnection networks. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2003, v:66, n:2, pp:129-134 [Journal]
  33. Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung
    Code compression by register operand dependency. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2004, v:72, n:3, pp:295-304 [Journal]
  34. Yung-Cheng Ma, Chung-Ping Chung
    A dominance relation enhanced branch-and-bound task allocation. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2001, v:58, n:2, pp:125-134 [Journal]
  35. Yung-Cheng Ma, Tien-Fu Chen, Chung-Ping Chung
    Posting file partitioning and parallel information retrieval. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2002, v:63, n:2, pp:113-127 [Journal]
  36. Yung-Cheng Ma, Jih-Ching Chiu, Tien-Fu Chen, Chung-Ping Chung
    Variable-size data item placement for load and storage balancing. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2003, v:66, n:2, pp:157-166 [Journal]
  37. R.-Ming Shiu, Neng-Pin Lu, Chung-Ping Chung
    Applying stack simulation for branch target buffers. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2000, v:52, n:1, pp:67-78 [Journal]
  38. Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung
    A software/hardware cooperated stack operations folding model for Java processors. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2004, v:72, n:3, pp:377-387 [Journal]
  39. Ren-Lianq Cheng, Chung-Ping Chung
    Reaching Approximate Agreement on Hypercube. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1993, v:19, n:7, pp:765-775 [Journal]
  40. Hong Chich Chou, Chung-Ping Chung
    A bound analysis of scheduling instructions on pipelined processors with a maximal delay of one cycle. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1992, v:18, n:4, pp:393-399 [Journal]
  41. Yuh-Horng Shiau, Chung-Ping Chung
    Adoptability and effectiveness of microcode compaction algorithms in superscalar processing. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1992, v:18, n:5, pp:497-510 [Journal]
  42. Kelvin Lin, Chung-Ping Chung, Jean Jyh-Jiun Shann
    Compressing MIPS code by multiple operand dependencies. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:4, pp:482-508 [Journal]
  43. Ching-Wen Chen, Chung-Ping Chung
    Designing A Disjoint Paths Interconnection Network with Fault Tolerance and Collision Solving. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2005, v:34, n:1, pp:63-80 [Journal]
  44. Hong Chich Chou, Chung-Ping Chung
    An Optimal Instruction Scheduler for Superscalar Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:3, pp:303-313 [Journal]
  45. Lee-Ren Ton, Lung-Chung Chang, Jean Jyh-Jiun Shann, Chung-Ping Chung
    Design of an optimal folding mechanism for Java processors. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2002, v:26, n:8, pp:341-352 [Journal]
  46. I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann
    Instruction Set Extension Generation with Considering Physical Constraints. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:291-305 [Conf]

  47. A Run-Time Reconfigurable Fabric for 3D Texture Filtering. [Citation Graph (, )][DBLP]


  48. ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor. [Citation Graph (, )][DBLP]


  49. Instruction Set Extension Exploration in Multiple-Issue Architecture. [Citation Graph (, )][DBLP]


  50. Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing. [Citation Graph (, )][DBLP]


  51. Smaller Split L-1 Data Caches for Multi-core Processing Systems. [Citation Graph (, )][DBLP]


  52. H-Buffer: An Efficient History-Based and Overflow Sharing Transparent Fragment Storage Method. [Citation Graph (, )][DBLP]


  53. Dynamic Reconfigurable Shaders with Load Balancing for Embedded Graphics Processing. [Citation Graph (, )][DBLP]


  54. Blocked-Z Test for Reducing Rasterization, Z Test and Shading Workloads. [Citation Graph (, )][DBLP]


  55. A Hierarchical Primitive Lists Structure for Tile-Based Rendering. [Citation Graph (, )][DBLP]


  56. Methods for Precise False-Overlap Detection in Tile-Based Rendering. [Citation Graph (, )][DBLP]


  57. iAIM: An Intelligent Autonomous Instruction Memory with Branch Handling Capability. [Citation Graph (, )][DBLP]


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