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Hidekazu Terai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Masaya Yoshikawa, Hidekazu Terai
    Co-evolutionary robotics using two kinds of neural networks. [Citation Graph (0, 0)][DBLP]
    CAINE, 2006, pp:330-334 [Conf]
  2. Masaya Yoshikawa, Masahiro Fukui, Hidekazu Terai
    Immune Algorithm Processor. [Citation Graph (0, 0)][DBLP]
    Computers and Their Applications, 2006, pp:13-18 [Conf]
  3. Yasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba
    Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:404-410 [Conf]
  4. Yasushi Ogawa, Hidekazu Terai, Tokinori Kozawa
    Automatic Layout Procedures for Serial Routing Devices. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:642-645 [Conf]
  5. Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno
    Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:262-269 [Conf]
  6. Hidekazu Terai, Fumio Goto, Katsuro Wakai, Tokinori Kozawa, Mitsugu Edagawa, Satoshi Hososaka, Masahiro Hashimoto
    Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:193-198 [Conf]
  7. Hidekazu Terai, Michiyoshi Hayase, Tokinori Kozawa
    A routing procedure for mixed array of custom macros and standard cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:503-508 [Conf]
  8. Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi
    VLSI processor architecture for real-time GA processing and PE-VLSI design. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2004, pp:625-628 [Conf]
  9. Masaya Yoshikawa, Hidekazu Terai
    A Hierarchical Parallel Placement Technique based on Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    ISDA, 2005, pp:302-307 [Conf]
  10. Masaya Yoshikawa, Hidekazu Terai
    Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique. [Citation Graph (0, 0)][DBLP]
    SERA, 2005, pp:130-136 [Conf]
  11. Masaya Yoshikawa, Hidekazu Terai
    Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing. [Citation Graph (0, 0)][DBLP]
    SERA, 2006, pp:95-100 [Conf]
  12. Masaya Yoshikawa, Hidekazu Terai
    Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation. [Citation Graph (0, 0)][DBLP]
    JACIII, 2006, v:10, n:1, pp:112-120 [Journal]
  13. Masaya Yoshikawa, Hidekazu Terai
    Architecture for high-speed Ant Colony Optimization. [Citation Graph (0, 0)][DBLP]
    IRI, 2007, pp:1-5 [Conf]
  14. Masaya Yoshikawa, Hidekazu Terai
    Performance driven placement technique based on collaboration of software and hardware. [Citation Graph (0, 0)][DBLP]
    Congress on Evolutionary Computation, 2005, pp:1570-1575 [Conf]

  15. Route selection algorithm based on integer operation Ant Colony Optimization. [Citation Graph (, )][DBLP]

  16. Dedicated Hardware for Ant Colony Optimization Using Distributed Memory. [Citation Graph (, )][DBLP]

  17. Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization. [Citation Graph (, )][DBLP]

  18. OX Hardware Engine for High Speed Character Inheritance. [Citation Graph (, )][DBLP]

  19. Car Navigation System Based on Hybrid Genetic Algorithm. [Citation Graph (, )][DBLP]

  20. Hybrid Architecture of Genetic Algorithm and Simulated Annealing. [Citation Graph (, )][DBLP]

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