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Dirk Fimmel:
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Publications of Author
- Jan Müller, Dirk Fimmel, Renate Merker
Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling. [Citation Graph (0, 0)][DBLP] Interaction between Compilers and Computer Architectures, 2004, pp:13-21 [Conf]
- Dirk Fimmel
Generation of Scheduling Functions Supporting LSGP-Partitioning. [Citation Graph (0, 0)][DBLP] ASAP, 2000, pp:349-0 [Conf]
- Dirk Fimmel, Renate Merker
Determination of the Processor Functionality in the Design of Processor Arrays. [Citation Graph (0, 0)][DBLP] ASAP, 1997, pp:199-208 [Conf]
- Renate Merker, Ulrich Eckhardt, Dirk Fimmel, H. Schreiber
A System for Designing Parallel Processor Arrays. [Citation Graph (0, 0)][DBLP] EUROCAST, 1997, pp:3-12 [Conf]
- Thomas Schmitt, Dirk Fimmel, Mathias Kortke, Renate Merker
Parallel Processor Array for Tomographic Reconstruction Algorithms. [Citation Graph (0, 0)][DBLP] EUROCAST, 1999, pp:127-141 [Conf]
- Mathias Kortke, Dirk Fimmel, Renate Merker
Parallelization of Algorithms for a System of Digital Signal Processors. [Citation Graph (0, 0)][DBLP] EUROMICRO, 1999, pp:1046-1050 [Conf]
- Dirk Fimmel, Renate Merker
Design of Processor Arrays for Real-Time Applications. [Citation Graph (0, 0)][DBLP] Euro-Par, 1998, pp:1018-1028 [Conf]
- Dirk Fimmel, Renate Merker
Localization of Data Transfer in Processor Arrays. [Citation Graph (0, 0)][DBLP] Euro-Par, 1999, pp:401-408 [Conf]
- Jan Müller, Dirk Fimmel, Renate Merker
Optimal Loop Scheduling with Register Constraints Using Flow Graphs. [Citation Graph (0, 0)][DBLP] ISPAN, 2004, pp:180-186 [Conf]
- Dirk Fimmel, Stefan Quitzk, Wolfgang Schwarz
Large-Scale Tolerance Analysis. [Citation Graph (0, 0)][DBLP] PARELEC, 2004, pp:33-38 [Conf]
- Dirk Fimmel, Renate Merker
Propagation of I/O-Variables in Massively Parallel Processor Arrays. [Citation Graph (0, 0)][DBLP] PDP, 1996, pp:501-509 [Conf]
- Dirk Fimmel, Jan Müller
Optimal Software Pipelining Under Register Constraints. [Citation Graph (0, 0)][DBLP] PDPTA, 2000, pp:- [Conf]
- Dirk Fimmel, Jan Müller
Optimal Software Pipelining with Rational Initiation Interval. [Citation Graph (0, 0)][DBLP] PDPTA, 2002, pp:638-643 [Conf]
- Dirk Fimmel, Jan Müller
Optimal Software Pipelining Under Resource Constraints. [Citation Graph (0, 0)][DBLP] Int. J. Found. Comput. Sci., 2001, v:12, n:6, pp:697-718 [Journal]
- Jan Müller, Dirk Fimmel, Renate Merker, Rainer Schaffer
A Hardware-Software System for Tomographic Reconstruction. [Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 2003, v:12, n:2, pp:203-0 [Journal]
- Dirk Fimmel, Renate Merker
Design of Processor Arrays for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP] The Journal of Supercomputing, 2001, v:19, n:1, pp:41-56 [Journal]
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