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Renate Merker: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jan Müller, Dirk Fimmel, Renate Merker
    Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:13-21 [Conf]
  2. Markus Rullmann, Renate Merker
    Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead. [Citation Graph (0, 0)][DBLP]
    ARCS Workshops, 2006, pp:132-141 [Conf]
  3. Dirk Fimmel, Renate Merker
    Determination of the Processor Functionality in the Design of Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:199-208 [Conf]
  4. Uwe Eckhardt, Renate Merker
    Scheduling in Co-Partitioned Array Architectures. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:219-228 [Conf]
  5. Sebastian Siegel, Renate Merker
    Optimized Data-Reuse in Processor Arrays. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:315-325 [Conf]
  6. Sebastian Siegel, Renate Merker
    Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy. [Citation Graph (0, 0)][DBLP]
    ASAP, 2006, pp:28-32 [Conf]
  7. Rainer Schaffer, Renate Merker, Francky Catthoor
    Causality Constraints for Processor Architectures with Sub-Word Parallelism. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:82-89 [Conf]
  8. Renate Merker, Ulrich Eckhardt, Dirk Fimmel, H. Schreiber
    A System for Designing Parallel Processor Arrays. [Citation Graph (0, 0)][DBLP]
    EUROCAST, 1997, pp:3-12 [Conf]
  9. Thomas Schmitt, Dirk Fimmel, Mathias Kortke, Renate Merker
    Parallel Processor Array for Tomographic Reconstruction Algorithms. [Citation Graph (0, 0)][DBLP]
    EUROCAST, 1999, pp:127-141 [Conf]
  10. Mathias Kortke, Dirk Fimmel, Renate Merker
    Parallelization of Algorithms for a System of Digital Signal Processors. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1046-1050 [Conf]
  11. Dirk Fimmel, Renate Merker
    Design of Processor Arrays for Real-Time Applications. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:1018-1028 [Conf]
  12. Dirk Fimmel, Renate Merker
    Localization of Data Transfer in Processor Arrays. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:401-408 [Conf]
  13. Sebastian Siegel, Renate Merker
    Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:1181-1191 [Conf]
  14. Markus Rullmann, Sebastian Siegel, Renate Merker
    Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  15. Markus Rullmann, Renate Merker
    Maximum edge matching for reconfigurable computing. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  16. Jan Müller, Dirk Fimmel, Renate Merker
    Optimal Loop Scheduling with Register Constraints Using Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ISPAN, 2004, pp:180-186 [Conf]
  17. Uwe Eckhardt, Renate Merker
    Optimization of the Background Memory Utilization by Partitioning. [Citation Graph (0, 0)][DBLP]
    ISSS, 1997, pp:82-89 [Conf]
  18. Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, Renate Merker, Jürgen Kelber
    A Parallel Hardware-Software System for Signal Processing Algorithms. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:215-220 [Conf]
  19. Mathias Kortke, Thomas Schmitt, Renate Merker
    Application of Partitioning Methods for the Design of Parallel Programs for a System of Digital Signal Processors. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2000, pp:139-143 [Conf]
  20. Renate Merker
    High-Level Synthesis System (HLDESA) for Processor Arrays. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2000, pp:89-93 [Conf]
  21. Rainer Schaffer, Renate Merker, Francky Catthoor
    Systematic Design of Programs with Sub-Word Parallelism. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2002, pp:393-398 [Conf]
  22. Sebastian Siegel, Renate Merker
    Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:85-90 [Conf]
  23. Rainer Schaffer, Renate Merker, Francky Catthoor
    Derivation of Packing Instructions for Exploiting Sub-Word Parallelism. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2006, pp:167-172 [Conf]
  24. Sebastian Siegel, Rainer Schaffer, Renate Merker
    Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2006, pp:173-180 [Conf]
  25. Dirk Fimmel, Renate Merker
    Propagation of I/O-Variables in Massively Parallel Processor Arrays. [Citation Graph (0, 0)][DBLP]
    PDP, 1996, pp:501-509 [Conf]
  26. Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys
    Co-Design of Massively Parallel Embedded Processor Architectures. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:27-34 [Conf]
  27. Rainer Schaffer, Renate Merker, Francky Catthoor
    Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:104-109 [Conf]
  28. Jan Müller, Dirk Fimmel, Renate Merker, Rainer Schaffer
    A Hardware-Software System for Tomographic Reconstruction. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:2, pp:203-0 [Journal]
  29. Rainer Schaffer, Francky Catthoor, Renate Merker
    Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. [Citation Graph (0, 0)][DBLP]
    Parallel Algorithms Appl., 2000, v:15, n:3-4, pp:201-228 [Journal]
  30. Uwe Eckhardt, Renate Merker
    Hierarchical algorithm partitioning at system level for an improved utilization of memory structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:1, pp:14-24 [Journal]
  31. Dirk Fimmel, Renate Merker
    Design of Processor Arrays for Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2001, v:19, n:1, pp:41-56 [Journal]
  32. Markus Rullmann, Renate Merker
    A Reconfiguration Aware Circuit Mapper for FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  33. Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
    Massively Parallel Processor Architectures: A Co-design Approach. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:61-68 [Conf]
  34. Rainer Schaffer, Renate Merker
    Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2006, pp:99-106 [Conf]

  35. Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. [Citation Graph (, )][DBLP]


  36. An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. [Citation Graph (, )][DBLP]


  37. Fine grain reconfigurable architectures. [Citation Graph (, )][DBLP]


  38. Systematic Generation of a Variety of Processor Arrays. [Citation Graph (, )][DBLP]


  39. A cost model for partial dynamic reconfiguration. [Citation Graph (, )][DBLP]


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