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Oliverio J. Santana: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Oliverio J. Santana, Alex Ramírez, Mateo Valero
    Reducing Fetch Architecture Complexity Using Procedure Inlining. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:97-106 [Conf]
  2. Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero
    Branch predictor guided instruction decoding. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:202-211 [Conf]
  3. Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
    Kilo-instruction processors, runahead and prefetching. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:269-278 [Conf]
  4. Adrián Cristal, Oliverio J. Santana, Mateo Valero
    Maintaining Thousands of In-flight Instructions. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:9-20 [Conf]
  5. Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero
    Studying New Ways for Improving Adaptive History Length Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:271-280 [Conf]
  6. Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero
    Tolerating Branch Predictor Latency on SMT. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:86-98 [Conf]
  7. Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero
    A Comprehensive Analysis of Indirect Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:133-145 [Conf]
  8. Alex Ramírez, Oliverio J. Santana, Josep-Lluis Larriba-Pey, Mateo Valero
    Fetching instruction streams. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:371-382 [Conf]
  9. Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero
    Kilo-Instruction Processors: Overcoming the Memory Wall. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:3, pp:48-57 [Journal]
  10. Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez
    Toward kilo-instruction processors. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:4, pp:389-417 [Journal]
  11. Oliverio J. Santana, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    A low-complexity fetch architecture for high-performance superscalar processors. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:2, pp:220-245 [Journal]
  12. Oliverio J. Santana, Alex Ramírez, Mateo Valero
    Enlarging Instruction Streams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:10, pp:1342-1357 [Journal]

  13. Runahead Threads: Reducing Resource Contention in SMT Processors. [Citation Graph (, )][DBLP]


  14. FAME: FAirly MEasuring Multithreaded Architectures. [Citation Graph (, )][DBLP]


  15. LPA: A First Approach to the Loop Processor Architecture. [Citation Graph (, )][DBLP]


  16. Runahead Threads to improve SMT performance. [Citation Graph (, )][DBLP]


  17. Code Semantic-Aware Runahead Threads. [Citation Graph (, )][DBLP]


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