The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Mateo Valero: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Oliverio J. Santana, Alex Ramírez, Mateo Valero
    Reducing Fetch Architecture Complexity Using Procedure Inlining. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2004, pp:97-106 [Conf]
  2. Jesús Corbal, Roger Espasa, Mateo Valero
    On the Efficiency of Reductions in µ-SIMD Media Extensions. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:83-0 [Conf]
  3. Jesús Corbal, Roger Espasa, Mateo Valero
    Command Vector Memory Systems: High Performance at Low Cost. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:68-0 [Conf]
  4. Daniel Ortega, Eduard Ayguadé, Jean-Loup Baer, Mateo Valero
    Cost-Effective Compiler Directed Memory Prefetching and Bypassing. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:189-198 [Conf]
  5. Daniel Ortega, Ivan Martel, Venkata Krishnan, Eduard Ayguadé, Mateo Valero
    Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multi-Threading Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:117-124 [Conf]
  6. Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    The Effect of Code Reordering on Branch Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:189-198 [Conf]
  7. F. Jesús Sánchez, Antonio González, Mateo Valero
    Static Locality Analysis for Cache Management. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:261-271 [Conf]
  8. Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero
    Branch predictor guided instruction decoding. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:202-211 [Conf]
  9. Luis Villa, Roger Espasa, Mateo Valero
    Effective Usage of Vector Registers in Advanced Vector Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:250-260 [Conf]
  10. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Architectural support for real-time task scheduling in SMT processors. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:166-176 [Conf]
  11. Esther Salamí, Jesús Corbal, Carlos Álvarez, Mateo Valero
    Cost effective memory disambiguation for multimedia codes. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:117-126 [Conf]
  12. Miguel Valero-García, Juan J. Navarro, José J. M. Liabería, Mateo Valero, Tomás Lang
    Mapping QR decomposition of a banded matrix on a ID systolic array with data contraflow and pipelined functional units. [Citation Graph (0, 0)][DBLP]
    Algorithms and Parallel VLSI Architectures, 1991, pp:25-38 [Conf]
  13. Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
    Speculative early register release. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:291-302 [Conf]
  14. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Predictable performance in SMT processors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:433-443 [Conf]
  15. Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero
    Kilo-instruction processors, runahead and prefetching. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:269-278 [Conf]
  16. Marco Galluzzi, Valentin Puente, Adrián Cristal, Ramón Beivide, José-Ángel Gregorio, Mateo Valero
    A first glance at Kilo-instruction based multiprocessors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:212-221 [Conf]
  17. Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé
    Using Sacks to Organize Registers in VLIW Machines. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1994, pp:628-639 [Conf]
  18. Mateo Valero, Montse Peiron, Eduard Ayguadé
    Memory Access Synchronization in Vector Multiprocessors. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1994, pp:414-425 [Conf]
  19. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Implicit vs. Explicit Resource Allocation in SMT Processors. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:44-51 [Conf]
  20. Jordi Torres, Eduard Ayguadé, Jesús Labarta, José M. Llabería, Mateo Valero
    On Automatic Loop Data-Mapping for Distributed-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    EDMCC, 1991, pp:173-182 [Conf]
  21. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Feasibility of QoS for SMT. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:535-540 [Conf]
  22. Adrián Cristal, Oliverio J. Santana, Mateo Valero
    Maintaining Thousands of In-flight Instructions. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:9-20 [Conf]
  23. Silvia M. Müller, Per Stenström, Mateo Valero, Stamatis Vassiliadis
    Parallel Computer Architecture. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:537-538 [Conf]
  24. Carlos Navarro, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    On the Performance of Fetch Engines Running DSS Workloads. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:940-949 [Conf]
  25. Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    Branch Prediction Using Profile Data. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:386-393 [Conf]
  26. Pascal Sainrat, Mateo Valero
    Instruction-Level Parallelism and Uniprocessor Architecture - Introduction. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:1241-1242 [Conf]
  27. Hans Vandierendonck, Alex Ramírez, Koenraad De Bosschere, Mateo Valero
    A Comparative Study of Redundancy in Trace Caches (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2002, pp:512-516 [Conf]
  28. Stamatis Vassiliadis, Francky Catthoor, Mateo Valero, Sorin Cotofana
    Topic 15+20: Multimedia and Embedded Systems. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:651-652 [Conf]
  29. Roger Espasa, Mateo Valero
    Decoupled Vector Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 1996, pp:281-290 [Conf]
  30. Roger Espasa, Mateo Valero
    Multithreaded Vector Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:237-0 [Conf]
  31. Ayose Falcón, Alex Ramírez, Mateo Valero
    A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:244-253 [Conf]
  32. Antonio González, José González, Mateo Valero
    Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:175-184 [Conf]
  33. Jesús Corbal, Roger Espasa, Mateo Valero
    DLP + TLP Processors for the Next Generation of Media Workloads. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:219-228 [Conf]
  34. Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
    Out-of-Order Commit Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:48-59 [Conf]
  35. Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    Trace Cache Redundancy: Red & Blue Traces. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:325-0 [Conf]
  36. Josep Llosa, Mateo Valero, Eduard Ayguadé
    Non-Consistent Dual Register Files to Reduce Register Pressure. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:22-31 [Conf]
  37. Marco A. Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa
    A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:647-653 [Conf]
  38. Carmelo Acosta, Ayose Falcón, Alex Ramírez, Mateo Valero
    A Complexity-Effective Simultaneous Multithreading Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:157-164 [Conf]
  39. David López, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:22-29 [Conf]
  40. Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
    Hardware Schemes for Early Register Release. [Citation Graph (0, 0)][DBLP]
    ICPP, 2002, pp:5-13 [Conf]
  41. Juan J. Navarro, José M. Llabería, Mateo Valero
    Solving Matrix Problems with No Size Restriction on a Systolic Array Processor. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:676-683 [Conf]
  42. Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas
    Optimization of Instruction Fetch for Decision Support Workloads. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:238-245 [Conf]
  43. Esther Salamí, Mateo Valero
    A Vector-µSIMD-VLIW Architecture for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    ICPP, 2005, pp:69-77 [Conf]
  44. Carlos Álvarez, Jesús Corbal, Esther Salamí, Mateo Valero
    On the potential of tolerant region reuse for multimedia applications. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:218-228 [Conf]
  45. Roger Espasa, Mateo Valero
    A Victim Cache for Vector Registers. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:293-300 [Conf]
  46. Roger Espasa, Mateo Valero, James E. Smith
    Vector Architectures: Past, Present and Future. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:425-432 [Conf]
  47. Antonio González, Carlos Aliagas, Mateo Valero
    A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1995, pp:338-347 [Conf]
  48. Rubén González, Adrián Cristal, Miquel Pericàs, Mateo Valero, Alexander V. Veidenbaum
    An asymmetric clustered processor based on value content. [Citation Graph (0, 0)][DBLP]
    ICS, 2005, pp:61-70 [Conf]
  49. Antonio González, Mateo Valero, Nigel P. Topham, Joan-Manuel Parcerisa
    Eliminating Cache Conflict Misses through XOR-Based Placement Functions. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:76-83 [Conf]
  50. David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
    Resource Widening Versus Replication: Limits and Performance-cost Trade-off. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:441-448 [Conf]
  51. David López, Mateo Valero, Josep Llosa, Eduard Ayguadé
    Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:12-19 [Conf]
  52. Ivan Martel, Daniel Ortega, Eduard Ayguadé, Mateo Valero
    Increasing effective IPC by exploiting distant parallelism. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:348-355 [Conf]
  53. Daniel Ortega, Eduard Ayguadé, Mateo Valero
    Dynamic memory instruction bypassing. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:316-325 [Conf]
  54. Daniel Ortega, Mateo Valero, Eduard Ayguadé
    A novel renaming mechanism that boosts software prefetching. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:501-510 [Conf]
  55. Montse Peiron, Mateo Valero, Eduard Ayguadé
    Synchronized access to streams in SIMD vector multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1994, pp:23-32 [Conf]
  56. Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
    Adding a vector unit to a superscalar processor. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:1-10 [Conf]
  57. Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Josep Torrellas, Mateo Valero
    Software trace cache. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:119-126 [Conf]
  58. Mateo Valero, Tomás Lang, Eduard Ayguadé
    Conflict-free access of vectors with power-of-two strides. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:149-156 [Conf]
  59. Luis Villa, Roger Espasa, Mateo Valero
    A Performance Study of Out-of-order Vector Architectures and Short Registers. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:37-44 [Conf]
  60. Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
    DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  61. Ayose Falcón, Alex Ramírez, Mateo Valero
    Effective Instruction Prefetching via Fetch Prestaging. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  62. Alex Pajuelo, Antonio González, Mateo Valero
    Control-Flow Independence Reuse via Dynamic Vectorization. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  63. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Hierarchical Clustered Register File Organization for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:77- [Conf]
  64. José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham
    Multiple-banked register file architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:316-325 [Conf]
  65. Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero
    Prophet/Critic Hybrid Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:250-263 [Conf]
  66. Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero
    A Content Aware Integer Register File Organization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:314-324 [Conf]
  67. José M. Llabería, Mateo Valero, Enrique Herrada Lillo, Jesús Labarta
    Analysis and Simulation of Multiplexed Single-Bus Networks With and Without Buffering. [Citation Graph (0, 0)][DBLP]
    ISCA, 1985, pp:414-421 [Conf]
  68. Alex Pajuelo, Antonio González, Mateo Valero
    Speculative Dynamic Vectorization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:271-280 [Conf]
  69. Montse Peiron, Mateo Valero, Eduard Ayguadé, Tomás Lang
    Vector Multiprocessors with Arbitrated Memory Access. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:243-252 [Conf]
  70. Juan J. Navarro, José M. Llabería, Mateo Valero
    Computing Size-Independent Matrix Problems on Systolic Array Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1986, pp:271-278 [Conf]
  71. Alex Ramírez, Luiz André Barroso, Kourosh Gharachorloo, Robert S. Cohn, Josep-Lluis Larriba-Pey, P. Geoffrey Lowney, Mateo Valero
    Code layout optimizations for transaction processing workloads. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:155-164 [Conf]
  72. Miguel Valero-García, Juan J. Navarro, José M. Llabería, Mateo Valero
    Systematic Hardware Adaptation of Systolic Algorithms. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:96-104 [Conf]
  73. Mateo Valero, Tomás Lang, José M. Llabería, Montse Peiron, Eduard Ayguadé, Juan J. Navarro
    Increasing the Number of Strides for Conflict-Free Vector Access. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:372-381 [Conf]
  74. Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero
    Improving Memory Latency Aware Fetch Policies for SMT Processors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:70-85 [Conf]
  75. Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero
    Kilo-instruction Processors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:10-25 [Conf]
  76. Ayose Falcón, Oliverio J. Santana, Pedro Medina, Enrique Fernández, Alex Ramírez, Mateo Valero
    Studying New Ways for Improving Adaptive History Length Branch Predictors. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:271-280 [Conf]
  77. Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero
    Tolerating Branch Predictor Latency on SMT. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:86-98 [Conf]
  78. Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
    Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:113-126 [Conf]
  79. Marco A. Ramírez, Adrián Cristal, Alexander V. Veidenbaum, Luis Villa, Mateo Valero
    A Simple Low-Energy Instruction Wakeup Mechanism. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2003, pp:99-112 [Conf]
  80. Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero
    A Comprehensive Analysis of Indirect Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2002, pp:133-145 [Conf]
  81. Sally A. McKee, Zhen Fang, Mateo Valero
    An MPEG-4 performance study for non-SIMD, general purpose architectures. [Citation Graph (0, 0)][DBLP]
    ISPASS, 2003, pp:49-57 [Conf]
  82. Mateo Valero
    Architectures for One Billion of Transistors. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:62- [Conf]
  83. Eduard Ayguadé, Jordi Garcia, Mercè Gironés, Jesús Labarta, Jordi Torres, Mateo Valero
    Detecting and Using Affinity in an Automatic Data Distribution Tool. [Citation Graph (0, 0)][DBLP]
    LCPC, 1994, pp:61-75 [Conf]
  84. Jesús Labarta, Eduard Ayguadé, Jordi Torres, Mateo Valero, José M. Llabería
    Balanced Loop Partitioning Using GTS. [Citation Graph (0, 0)][DBLP]
    LCPC, 1991, pp:298-312 [Conf]
  85. Jordi Torres, Eduard Ayguadé, Jesús Labarta, Mateo Valero
    Align and Distribute-based Linear Loop Transformations. [Citation Graph (0, 0)][DBLP]
    LCPC, 1993, pp:321-339 [Conf]
  86. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    MIRS: Modulo Scheduling with Integrated Register Spilling. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:239-253 [Conf]
  87. Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández
    Dynamically Controlled Resource Allocation in SMT Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:171-182 [Conf]
  88. Jesús Corbal, Roger Espasa, Mateo Valero
    Three-dimensional memory vectorization for high bandwidth media memory systems. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:149-160 [Conf]
  89. Jesús Corbal, Roger Espasa, Mateo Valero
    Exploiting a New Level of DLP in Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:72-0 [Conf]
  90. Roger Espasa, Mateo Valero, James E. Smith
    Out-of-Order Vector Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:160-170 [Conf]
  91. Jorge García, Jesús Corbal, Llorenç Cerdà, Mateo Valero
    Design and Implementation of High-Performance Memory Systems for Future Packet Buffers. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:373-386 [Conf]
  92. Josep Llosa, Mateo Valero, Eduard Ayguadé
    Heuristics for Register-Constrained Software Pipelining. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:250-261 [Conf]
  93. Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
    Hypernode reduction modulo scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:350-360 [Conf]
  94. David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
    Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:237-246 [Conf]
  95. Alex Ramírez, Oliverio J. Santana, Josep-Lluis Larriba-Pey, Mateo Valero
    Fetching instruction streams. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:371-382 [Conf]
  96. Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
    Delaying Physical Register Allocation through Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:186-0 [Conf]
  97. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Two-level hierarchical register file organization for VLIW processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:137-146 [Conf]
  98. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Modulo scheduling with integrated register spilling for clustered VLIW architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:160-169 [Conf]
  99. Miquel Pericàs, Rubén González, Adrián Cristal, Alexander V. Veidenbaum, Mateo Valero
    An Optimized Front-End Physical Register File with Banking and Writeback Filtering. [Citation Graph (0, 0)][DBLP]
    PACS, 2004, pp:1-14 [Conf]
  100. Roger Espasa, Mateo Valero, David A. Padua, Marta Jiménez, Eduard Ayguadé
    Quantitative analysis of vector code. [Citation Graph (0, 0)][DBLP]
    PDP, 1995, pp:452-463 [Conf]
  101. Jordi Torres, Eduard Ayguadé, Jesús Labarta, Mateo Valero
    Loop Parallelization: Revisiting Framework of Unimodular Transformations. [Citation Graph (0, 0)][DBLP]
    PDP, 1996, pp:420-428 [Conf]
  102. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Improved spill code generation for software pipelined loops. [Citation Graph (0, 0)][DBLP]
    PLDI, 2000, pp:134-144 [Conf]
  103. Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero
    with Wide Functional Units. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:88-97 [Conf]
  104. Esther Salamí, Mateo Valero
    Initial Evaluation of Multimedia Extensions on VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:403-412 [Conf]
  105. Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
    A cost effective architecture for vectorizable numerical and multimedia applications. [Citation Graph (0, 0)][DBLP]
    SPAA, 2001, pp:103-112 [Conf]
  106. Francisca Quintana, Roger Espasa, Mateo Valero
    An ISA Comparison Between Superscalar and Vector Processors. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1998, pp:548-560 [Conf]
  107. Luis Villa, Roger Espasa, Mateo Valero
    Registers Size Influence on Vector Architectures. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1998, pp:439-451 [Conf]
  108. Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero
    Evaluating kilo-instruction multiprocessors. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:72-79 [Conf]
  109. Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero
    Architectural impact of stateful networking applications. [Citation Graph (0, 0)][DBLP]
    ANCS, 2005, pp:11-18 [Conf]
  110. Carlos Álvarez, Jesús Corbal, Esther Salamí, Mateo Valero
    Initial Results on Fuzzy Floating Point Computation for Multimedia Processors. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2002, v:1, n:, pp:- [Journal]
  111. Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
    A Case for Resource-conscious Out-of-order Processors. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
  112. Sriram Vajapeyam, Mateo Valero
    Early 21st Century Processors - Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2001, v:34, n:4, pp:47-50 [Journal]
  113. Josep Llosa, Eduard Ayguadé, Mateo Valero
    Quantitative Evaluation of Register Pressure on Software Pipelined Loops. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:2, pp:121-142 [Journal]
  114. Daniel Ortega, Mateo Valero, Eduard Ayguadé
    Dynamic Memory Instruction Bypassing. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2004, v:32, n:3, pp:199-224 [Journal]
  115. Alex Ramírez, Josep-Lluis Larriba-Pey, Carlos Navarro, Mateo Valero, Josep Torrellas
    Software Trace Cache for Commercial Applications. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2002, v:30, n:5, pp:373-395 [Journal]
  116. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2004, v:32, n:6, pp:447-474 [Journal]
  117. Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
    Dynamic Register Renaming Through Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  118. Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero
    Kilo-Instruction Processors: Overcoming the Memory Wall. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:3, pp:48-57 [Journal]
  119. Ayose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero
    Better Branch Prediction Through Prophet/Critic Hybrids. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2005, v:25, n:1, pp:80-89 [Journal]
  120. Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández
    QoS for High-Performance SMT Processors in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:4, pp:24-31 [Journal]
  121. Francisca Quintana, Jesús Corbal, Roger Espasa, Mateo Valero
    A Cost-Effective Architecture for Vectorizable Numerical and Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    Theory Comput. Syst., 2003, v:36, n:5, pp:575-593 [Journal]
  122. Mateo Valero, Eduard Ayguadé, Montse Peiron
    Network Synchronization and Out-of-Order Access to Vectors. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1994, v:4, n:, pp:405-415 [Journal]
  123. Mateo Valero, Tomás Lang, José María Llabería, Montse Peiron, Juan J. Navarro, Eduard Ayguadé
    Conflict-Free Strides for Vectors in Matched Memories. [Citation Graph (0, 0)][DBLP]
    Parallel Processing Letters, 1991, v:1, n:, pp:95-102 [Journal]
  124. Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
    A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:3-10 [Journal]
  125. Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, Llorenc Cruz, Fernando Latorre, Antonio González, Mateo Valero
    Errata on "Measuring Experimental Error in Microprocessor Simulation". [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2002, v:30, n:1, pp:2-4 [Journal]
  126. Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero
    The impact of traffic aggregation on the memory performance of networking applications. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:57-62 [Journal]
  127. Alex Pajuelo, Antonio González, Mateo Valero
    Speculative execution for hiding memory latency. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:49-56 [Journal]
  128. Adrián Cristal, Oliverio J. Santana, Mateo Valero, José F. Martínez
    Toward kilo-instruction processors. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:4, pp:389-417 [Journal]
  129. Esther Salamí, Mateo Valero
    Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:2, pp:199-219 [Journal]
  130. Oliverio J. Santana, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    A low-complexity fetch architecture for high-performance superscalar processors. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:2, pp:220-245 [Journal]
  131. Carlos Álvarez, Jesús Corbal, Mateo Valero
    Fuzzy Memoization for Floating-Point Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:922-927 [Journal]
  132. Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero
    Predictable Performance in SMT Processors: Synergy between the OS and SMTs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:7, pp:785-799 [Journal]
  133. Miguel Angel Fiol, J. Luis A. Yebra, Ignacio Alegre, Mateo Valero
    A Discrete Optimization Problem in Local Networks and Data Alignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:6, pp:702-713 [Journal]
  134. Jorge García-Vidal, Maribel March, Llorenç Cerdà, Jesús Corbal, Mateo Valero
    A DRAM/SRAM Memory Scheme for Fast Packet Buffers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:5, pp:588-602 [Journal]
  135. Tomás Lang, Mateo Valero, Ignacio Alegre
    Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:12, pp:1227-1234 [Journal]
  136. Tomás Lang, Mateo Valero, Miguel Angel Fiol
    Reduction of Connections for Multibus Organization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:8, pp:707-716 [Journal]
  137. Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt
    Lifetime-Sensitive Modulo Scheduling in a Production Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:3, pp:234-249 [Journal]
  138. Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
    Modulo Scheduling with Reduced Register Pressure. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:6, pp:625-638 [Journal]
  139. David López, Josep Llosa, Mateo Valero, Eduard Ayguadé
    Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:10, pp:1033-1051 [Journal]
  140. Veljko M. Milutinovic, Mateo Valero
    Enhancing and Exploiting the Locality. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:97-99 [Journal]
  141. Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero
    Late Allocation and Early Release of Physical Registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:10, pp:1244-1259 [Journal]
  142. Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
    Software Trace Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:1, pp:22-35 [Journal]
  143. Mateo Valero, Tomás Lang, Montse Peiron, Eduard Ayguadé
    Conflict-Free Access for Streams in Multimodule Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:5, pp:634-646 [Journal]
  144. Roger Espasa, Mateo Valero
    A Simulation Study of Decoupled Vector Architectures. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 1999, v:14, n:2, pp:124-152 [Journal]
  145. Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
    Register Constrained Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:5, pp:417-430 [Journal]
  146. Marco Galluzzi, Enrique Vallejo, Adrián Cristal, Fernando Vallejo, Ramón Beivide, Per Stenström, James E. Smith, Mateo Valero
    Implicit Transactional Memory in Kilo-Instruction Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:339-353 [Conf]
  147. Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
    Microarchitectural Support for Speculative Register Renaming. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-10 [Conf]
  148. Francisco J. Cazorla, Enrique Fernández, Peter M. W. Knijnenburg, Alex Ramírez, Rizos Sakellariou, Mateo Valero
    On the Problem of Minimizing Workload Execution Time in SMT Processors. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:66-73 [Conf]
  149. Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero
    Online Prediction of Applications Cache Utility. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:169-177 [Conf]
  150. Friman Sánchez, Esther Salamí, Alex Ramírez, Mateo Valero
    Performance Analysis of Sequence Alignment Applications. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:51-60 [Conf]
  151. Tim Harris, Adrián Cristal, Osman S. Unsal, Eduard Ayguadé, Fabrizio Gagliardi, Burton Smith, Mateo Valero
    Transactional Memory: An Overview. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:3, pp:8-29 [Journal]
  152. Oliverio J. Santana, Alex Ramírez, Mateo Valero
    Enlarging Instruction Streams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:10, pp:1342-1357 [Journal]

  153. A Flexible Heterogeneous Multi-Core Architecture. [Citation Graph (, )][DBLP]


  154. Runahead Threads: Reducing Resource Contention in SMT Processors. [Citation Graph (, )][DBLP]


  155. FAME: FAirly MEasuring Multithreaded Architectures. [Citation Graph (, )][DBLP]


  156. MLP-Aware Dynamic Cache Partitioning. [Citation Graph (, )][DBLP]


  157. ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. [Citation Graph (, )][DBLP]


  158. Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation. [Citation Graph (, )][DBLP]


  159. Exploiting Inactive Rename Slots for Detecting Soft Errors. [Citation Graph (, )][DBLP]


  160. Quantitative analysis of sequence alignment applications on multiprocessor architectures. [Citation Graph (, )][DBLP]


  161. Load balancing using dynamic cache allocation. [Citation Graph (, )][DBLP]


  162. The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. [Citation Graph (, )][DBLP]


  163. Oblivious routing schemes in extended generalized Fat Tree networks. [Citation Graph (, )][DBLP]


  164. Hardware Transactional Memory with Operating System Support, HTMOS. [Citation Graph (, )][DBLP]


  165. Long DNA Sequence Comparison on Multicore Architectures. [Citation Graph (, )][DBLP]


  166. Architecture Performance Prediction Using Evolutionary Artificial Neural Networks. [Citation Graph (, )][DBLP]


  167. MLP-Aware Dynamic Cache Partitioning. [Citation Graph (, )][DBLP]


  168. Supercomputing for the Future, Supercomputing from the Past (Keynote). [Citation Graph (, )][DBLP]


  169. LPA: A First Approach to the Loop Processor Architecture. [Citation Graph (, )][DBLP]


  170. Runahead Threads to improve SMT performance. [Citation Graph (, )][DBLP]


  171. A decoupled KILO-instruction processor. [Citation Graph (, )][DBLP]


  172. Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory. [Citation Graph (, )][DBLP]


  173. MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors. [Citation Graph (, )][DBLP]


  174. Code Semantic-Aware Runahead Threads. [Citation Graph (, )][DBLP]


  175. A european perspective on supercomputing. [Citation Graph (, )][DBLP]


  176. Exploring pattern-aware routing in generalized fat tree networks. [Citation Graph (, )][DBLP]


  177. QuakeTM: parallelizing a complex sequential application using transactional memory. [Citation Graph (, )][DBLP]


  178. Overlapping communication and computation by using a hybrid MPI/SMPSs approach. [Citation Graph (, )][DBLP]


  179. Balancing HPC applications through smart allocation of resources in MT processors. [Citation Graph (, )][DBLP]


  180. Clock gate on abort: Towards energy-efficient hardware Transactional Memory. [Citation Graph (, )][DBLP]


  181. Power-aware load balancing of large scale MPI applications. [Citation Graph (, )][DBLP]


  182. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. [Citation Graph (, )][DBLP]


  183. Software-Controlled Priority Characterization of POWER5 Processor. [Citation Graph (, )][DBLP]


  184. A Two-Level Load/Store Queue Based on Execution Locality. [Citation Graph (, )][DBLP]


  185. Hardware support for WCET analysis of hard real-time multicore systems. [Citation Graph (, )][DBLP]


  186. Performance Analysis of a New Packet Trace Compressor based on TCP Flow Clustering. [Citation Graph (, )][DBLP]


  187. Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications. [Citation Graph (, )][DBLP]


  188. On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications. [Citation Graph (, )][DBLP]


  189. Simulation environment for studying overlap of communication and computation. [Citation Graph (, )][DBLP]


  190. A distributed processor state management architecture for large-window processors. [Citation Graph (, )][DBLP]


  191. Characterizing the resource-sharing levels in the UltraSPARC T2 processor. [Citation Graph (, )][DBLP]


  192. EazyHTM: eager-lazy hardware transactional memory. [Citation Graph (, )][DBLP]


  193. Thread to strand binding of parallel network applications in massive multi-threaded systems. [Citation Graph (, )][DBLP]


  194. Debugging programs that use atomic blocks and transactional memory. [Citation Graph (, )][DBLP]


  195. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. [Citation Graph (, )][DBLP]


  196. Atomic quake: using transactional memory in an interactive multiplayer game server. [Citation Graph (, )][DBLP]


  197. Effective communication and computation overlap with hybrid MPI/SMPSs. [Citation Graph (, )][DBLP]


  198. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. [Citation Graph (, )][DBLP]


  199. Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. [Citation Graph (, )][DBLP]


  200. Measuring Operating System Overhead on CMT Processors. [Citation Graph (, )][DBLP]


  201. Thread to Core Assignment in SMT On-Chip Multiprocessors. [Citation Graph (, )][DBLP]


  202. A dynamic scheduler for balancing HPC applications. [Citation Graph (, )][DBLP]


  203. A performance evaluation of the multiple bus network for multiprocessor systems. [Citation Graph (, )][DBLP]


  204. Vectorized AES Core for High-throughput Secure Environments. [Citation Graph (, )][DBLP]


  205. MultiLayer processing - an execution model for parallel stateful packet processing. [Citation Graph (, )][DBLP]


  206. Evolutionary system for prediction and optimization of hardware architecture performance. [Citation Graph (, )][DBLP]


  207. Transactional Memory and OpenMP. [Citation Graph (, )][DBLP]


  208. Scalability Analysis of Progressive Alignment on a Multicore. [Citation Graph (, )][DBLP]


  209. Explaining Dynamic Cache Partitioning Speed Ups. [Citation Graph (, )][DBLP]


  210. Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors. [Citation Graph (, )][DBLP]


Search in 0.178secs, Finished in 0.189secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002