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Dean M. Tullsen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John S. Seng, Dean M. Tullsen
    The Effect of Compiler Optimizations on Pentium 4 Power Consumption. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2003, pp:51-56 [Conf]
  2. Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
    Core architecture optimization for heterogeneous chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    PACT, 2006, pp:23-32 [Conf]
  3. Nathan Tuck, Dean M. Tullsen
    Initial Observations of the Simultaneous Multithreading Pentium 4 Processor. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2003, pp:26-0 [Conf]
  4. Eric Tune, Dean M. Tullsen, Brad Calder
    Quantifying Instruction Criticality. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:104-0 [Conf]
  5. Weifeng Zhang, Brad Calder, Dean M. Tullsen
    An Event-Driven Multithreaded Dynamic Optimization Framework. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:87-98 [Conf]
  6. Allan Snavely, Dean M. Tullsen
    Symbiotic Jobscheduling for a Simultaneous Multithreading Processor. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2000, pp:234-244 [Conf]
  7. Weifeng Zhang, Brad Calder, Dean M. Tullsen
    A Self-Repairing Prefetcher in an Event-Driven Dynamic Optimization Framework. [Citation Graph (0, 0)][DBLP]
    CGO, 2006, pp:50-64 [Conf]
  8. Dean M. Tullsen
    Fellowship - Simulation And Modeling Of A Simultaneous Multithreading Processor. [Citation Graph (0, 0)][DBLP]
    Int. CMG Conference, 1996, pp:819-828 [Conf]
  9. Nathan Tuck, Dean M. Tullsen
    Multithreaded Value Prediction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:5-15 [Conf]
  10. Dean M. Tullsen, Guang R. Gao
    Multithreaded Execution Architecture and Compilation. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:321- [Conf]
  11. Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy
    Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:54-58 [Conf]
  12. Eric Tune, Dongning Liang, Dean M. Tullsen, Brad Calder
    Dynamic Prediction of Critical Path Instructions. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:185-196 [Conf]
  13. Steven Wallace, Dean M. Tullsen, Brad Calder
    Instruction Recycling on a Multiple-Path Processor. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:44-53 [Conf]
  14. David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen
    Application-specific customization of parameterized FPGA soft-core processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:261-268 [Conf]
  15. David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky
    Conjoining soft-core FPGA processors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:694-701 [Conf]
  16. John S. Seng, Dean M. Tullsen, George Cai
    Power-Sensitive Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:199-0 [Conf]
  17. Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary S. Tyson, Todd M. Austin
    Classifying load and store instructions for memory renaming. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:399-407 [Conf]
  18. Jamison D. Collins, Dean M. Tullsen
    Clustered Multithreaded Architectures - Pursuing both IPC and Cycle Time. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  19. M. De Vuyst, Rakesh Kumar, Dean M. Tullsen
    Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  20. Florin Baboescu, Dean M. Tullsen, Grigore Rosu, Sumeet Singh
    A Tree Based Router Search Engine Architecture with Single Port Memories. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:123-133 [Conf]
  21. Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen
    Speculative precomputation: long-range prefetching of delinquent loads. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:14-25 [Conf]
  22. Brad Calder, Glenn Reinman, Dean M. Tullsen
    Selective Value Prediction. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:64-74 [Conf]
  23. Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas
    Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:64-75 [Conf]
  24. Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
    Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:408-419 [Conf]
  25. Dean M. Tullsen, Susan J. Eggers
    Limitations of Cache Prefetching on a Bus-Based Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1993, pp:278-288 [Conf]
  26. Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm
    Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1996, pp:191-202 [Conf]
  27. Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
    Simultaneous Multithreading: Maximizing On-Chip Parallelism. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:392-403 [Conf]
  28. Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
    Retrospective: Simultaneous Multithreading: Maximizing On-Chip Parallelism. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:115-116 [Conf]
  29. Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
    Simultaneous Multithreading: Maximizing On-Chip Parallelism. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:533-544 [Conf]
  30. Dean M. Tullsen, John S. Seng
    Storageless Value Prediction Using Prior Register Values. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:270-279 [Conf]
  31. Steven Wallace, Brad Calder, Dean M. Tullsen
    Threaded Multiple Path Execution. [Citation Graph (0, 0)][DBLP]
    ISCA, 1998, pp:238-249 [Conf]
  32. Barbara Kreaseck, Dean M. Tullsen, Brad Calder
    Limits of Task-Based Parallelism in Irregular Applications. [Citation Graph (0, 0)][DBLP]
    ISHPC, 2000, pp:43-58 [Conf]
  33. Jamison D. Collins, Suleyman Sair, Brad Calder, Dean M. Tullsen
    Pointer cache assisted prefetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:62-73 [Conf]
  34. Jamison D. Collins, Dean M. Tullsen
    Hardware Identification of Cache Conflict Misses. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:126-135 [Conf]
  35. Jamison D. Collins, Dean M. Tullsen, Hong Wang
    Control Flow Optimization Via Dynamic Reconvergence Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:129-140 [Conf]
  36. Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen
    Dynamic speculative precomputation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:306-317 [Conf]
  37. Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
    Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:81-92 [Conf]
  38. Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen
    Conjoined-Core Chip Multiprocessing. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:195-206 [Conf]
  39. Rakesh Kumar, Dean M. Tullsen
    Compiling for instruction cache performance on a multithreaded architecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:419-429 [Conf]
  40. Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen
    Tuning Compiler Optimizations for Simultaneous Multithreading. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:114-124 [Conf]
  41. John S. Seng, Eric Tune, Dean M. Tullsen
    Reducing power with dynamic critical path information. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:114-123 [Conf]
  42. Dean M. Tullsen, Jeffery A. Brown
    Handling long-latency loads in a simultaneous multithreading processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:318-327 [Conf]
  43. Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder
    Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:183-194 [Conf]
  44. John S. Seng, Dean M. Tullsen
    Exploring the Potential of Architecture-Level Power Optimizations. [Citation Graph (0, 0)][DBLP]
    PACS, 2003, pp:132-147 [Conf]
  45. Carlos García Quiñones, Carlos Madriles, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen
    Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:269-279 [Conf]
  46. Allan Snavely, Dean M. Tullsen, Geoffrey M. Voelker
    Symbiotic jobscheduling with priorities for a simultaneous multithreading processor. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2002, pp:66-76 [Conf]
  47. Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
    Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
  48. Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan
    Heterogeneous Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:11, pp:32-38 [Journal]
  49. Jack L. Lo, Susan J. Eggers, Henry M. Levy, Sujay S. Parekh, Dean M. Tullsen
    Tuning Compiler Optimizations for Simultaneous Multithreading. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:6, pp:477-503 [Journal]
  50. Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen
    Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05). [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:4, pp:4- [Journal]
  51. Brad Calder, Dean M. Tullsen
    Introduction. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:1, pp:1-2 [Journal]
  52. Brad Calder, Dean M. Tullsen
    Introduction. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:1, pp:1-2 [Journal]
  53. Brad Calder, Dean M. Tullsen
    Introduction. [Citation Graph (0, 0)][DBLP]
    TACO, 2006, v:3, n:1, pp:1-2 [Journal]
  54. Jamison D. Collins, Dean M. Tullsen
    Runtime identification of cache conflict misses: The adaptive miss buffer. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2001, v:19, n:4, pp:413-439 [Journal]
  55. Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen
    Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1997, v:15, n:3, pp:322-354 [Journal]
  56. Dean M. Tullsen, Susan J. Eggers
    Effective Cache Prefetching on Bus-Based Multiprocessors [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1995, v:13, n:1, pp:57-88 [Journal]
  57. Jack L. Lo, Sujay S. Parekh, Susan J. Eggers, Henry M. Levy, Dean M. Tullsen
    Software-Directed Register Deallocation for Simultaneous Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:9, pp:922-933 [Journal]
  58. Dean M. Tullsen
    HCW Keynote Address Holistic Design of Multi-Core Architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1- [Conf]
  59. Jeffery A. Brown, Rakesh Kumar, Dean M. Tullsen
    Proximity-aware directory-based coherence for multi-core processor architectures. [Citation Graph (0, 0)][DBLP]
    SPAA, 2007, pp:126-134 [Conf]
  60. Brad Calder, Dean M. Tullsen
    Introduction. [Citation Graph (0, 0)][DBLP]
    TACO, 2007, v:4, n:1, pp:- [Journal]
  61. Ravi Iyer, Dean M. Tullsen
    Editorial: Special Section on CMP Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1025-1027 [Journal]

  62. Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading. [Citation Graph (, )][DBLP]


  63. Accurate branch prediction for short threads. [Citation Graph (, )][DBLP]


  64. Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture. [Citation Graph (, )][DBLP]


  65. Accelerating and Adapting Precomputation Threads for Effcient Prefetching. [Citation Graph (, )][DBLP]


  66. Speculative Code Value Specialization Using the Trace Cache Fill Unit. [Citation Graph (, )][DBLP]


  67. The shared-thread multiprocessor. [Citation Graph (, )][DBLP]


  68. Creating artificial global history to improve branch prediction accuracy. [Citation Graph (, )][DBLP]


  69. Dynamic workload characterization for power efficient scheduling on CMP systems. [Citation Graph (, )][DBLP]


  70. Holistic Design of Multiple-Core Architectures. [Citation Graph (, )][DBLP]


  71. McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. [Citation Graph (, )][DBLP]


  72. Reducing peak power with a table-driven adaptive processor core. [Citation Graph (, )][DBLP]


  73. Software data spreading: leveraging distributed caches to improve single thread performance. [Citation Graph (, )][DBLP]


  74. Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors. [Citation Graph (, )][DBLP]


  75. The architecture of Efficient Multi-Core Processors: A Holistic Approach. [Citation Graph (, )][DBLP]


  76. The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best. [Citation Graph (, )][DBLP]


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