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John Paul Shen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. R. David Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen
    Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2002, pp:57-67 [Conf]
  2. Bohuslav Rychlik, John Faistl, Bryon Krug, John Paul Shen
    Efficacy and Performance Impact of Value Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:148-0 [Conf]
  3. Andrew S. Huang, John Paul Shen
    The Intrinsic Bandwidth Requirements of Ordinary Programs. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1996, pp:105-114 [Conf]
  4. Mikko H. Lipasti, Christopher B. Wilkerson, John Paul Shen
    Value Locality and Load Value Prediction. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1996, pp:138-147 [Conf]
  5. Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
    Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 2004, pp:144-155 [Conf]
  6. Andrew Wolfe, John Paul Shen
    A Variable Instruction Stream Extension to the VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1991, pp:2-14 [Conf]
  7. Dongkeun Kim, Shih-wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar, John Paul Shen
    Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:27-38 [Conf]
  8. Mauricio Breternitz Jr., John Paul Shen
    Architecture Synthesis of High-Performance Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:542-548 [Conf]
  9. Alexander G. Dean, John Paul Shen
    Hardware to Software Migration with Real-Time Thread Integration. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10243-0 [Conf]
  10. Yuan C. Chou, Daniel P. Siewiorek, John Paul Shen
    A Realistic Study on Multithreaded Superscalar Processor Design. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:1092-1101 [Conf]
  11. Jonathan Combs, Candice Bechem Combs, John Paul Shen
    Mispredicted Path Cache Effects. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1999, pp:1322-1231 [Conf]
  12. Mikko H. Lipasti, John Paul Shen
    The Performance Potential of Value and Dependence Prediction. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:1043-1052 [Conf]
  13. John Paul Shen
    Highlights of CMU Research on CAD, CAM, CAT of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    FJCC, 1986, pp:878-889 [Conf]
  14. Trung A. Diep, John Paul Shen
    Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:100-109 [Conf]
  15. Scott H. Robinson, John Paul Shen
    Direct Methods for Synthesis of Self-Monitoring State Machines. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:306-315 [Conf]
  16. Michael A. Schuette, John Paul Shen
    Exploiting Instruction-Level Resource Parallelism for Transparent, Integrated Control-Flow Monitoring. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:318-325 [Conf]
  17. Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen
    Hardware Support for Prescient Instruction Prefetch. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:84-95 [Conf]
  18. Derek B. Noonburg, John Paul Shen
    A Framework for Statistical Modeling of Superscalar Processor Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:298-309 [Conf]
  19. Ryan Rakvic, Bryan Black, Deepak Limaye, John Paul Shen
    Non-Vital Loads. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:165-0 [Conf]
  20. Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen
    Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:187-196 [Conf]
  21. Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen
    Register Renaming and Scheduling for Dynamic Execution of Predicated Code. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:15-26 [Conf]
  22. Scott H. Robinson, John Paul Shen
    Evaluation and Synthesis of Self-Monitoring State Machines. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:276-279 [Conf]
  23. Murali Annavaram, Trung A. Diep, John Paul Shen
    Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:242-248 [Conf]
  24. Bryan Black, Andrew S. Huang, Mikko H. Lipasti, John Paul Shen
    Can Trace-Driven Simulators Accurately Predict Superscalar Performance? [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:478-485 [Conf]
  25. Trung A. Diep, Mikko H. Lipasti, John Paul Shen
    Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:86-93 [Conf]
  26. Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang
    Best of Both Latency and Throughput. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:236-243 [Conf]
  27. Deepak Limaye, Ryan Rakvic, John Paul Shen
    Parallel Cachelets. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:284-292 [Conf]
  28. John Paul Shen
    Clear and Present Tensions in Microprocessor Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:4-4 [Conf]
  29. David C. H. Lee, John Paul Shen
    Easily-Testable (N, K) Shuffle/Exchange Networks. [Citation Graph (0, 0)][DBLP]
    ICPP, 1983, pp:65-70 [Conf]
  30. Bryan Black, Brian Mueller, Stephanie Postal, Ryan Rakvic, Noppanunt Utamaphethai, John Paul Shen
    Load Execution Latency Reduction. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:29-36 [Conf]
  31. Yuan C. Chou, Jason Fung, John Paul Shen
    Reducing branch misprediction penalties via dynamic control independence detection. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:109-118 [Conf]
  32. Chris J. Newburn, Andrew S. Huang, John Paul Shen
    Balancing Fine- and Medium-Grained Parallelism in Scheduling Loops for the XIMD Architecture. [Citation Graph (0, 0)][DBLP]
    Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993, pp:39-52 [Conf]
  33. Chris J. Newburn, Derek B. Noonburg, John Paul Shen
    A PDG-based Tool and its Use in Analyzing Program Control Dependences. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:157-168 [Conf]
  34. Satish Narayanasamy, Hong Wang, Perry H. Wang, John Paul Shen, Brad Calder
    A Dependency Chain Clustered Microarchitecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  35. Murali Annavaram, Ed Grochowski, John Paul Shen
    Mitigating Amdahl's Law through EPI Throttling. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:298-309 [Conf]
  36. Bryan Black, Bohuslav Rychlik, John Paul Shen
    The Block-Based Trace Cache. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:196-207 [Conf]
  37. Andrew Wolfe, Mauricio Breternitz Jr., Chriss Stephens, A. L. Ting, D. B. Kirk, Ronald P. Bianchini Jr., John Paul Shen
    The White Dwarf: A High-Performance Application-Specific Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:212-222 [Conf]
  38. Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen
    Speculative precomputation: long-range prefetching of delinquent loads. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:14-25 [Conf]
  39. Yuan C. Chou, John Paul Shen
    Instruction path coprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:270-281 [Conf]
  40. Trung A. Diep, Christopher Nelson, John Paul Shen
    Performance Evaluation of the PowerPC 620 Microarchitecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:163-175 [Conf]
  41. Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan Rakvic, Hong Wang, John Paul Shen
    Multiple Instruction Stream Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:114-127 [Conf]
  42. Andrew S. Huang, Gert Slavenburg, John Paul Shen
    Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:200-210 [Conf]
  43. Ryan Rakvic, Bryan Black, John Paul Shen
    Completion time multiple branch prediction for enhancing trace cache performance. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:47-58 [Conf]
  44. John Paul Shen, John P. Hayes
    Fault Tolerance of a Class of Connecting Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 1980, pp:61-71 [Conf]
  45. Chriss Stephens, Bryce Cogswell, John Heinlein, Gregory Palmer, John Paul Shen
    Instruction Level Profiling and Evaluation of the IBM/6000. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:180-189 [Conf]
  46. Patrick P. Fasang, Michael A. Schuette, John Paul Shen, William A. Gwaltney
    Automated Design for Testability of Semicustom Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:558-564 [Conf]
  47. Wojciech Maly, F. Joel Ferguson, John Paul Shen
    Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:390-399 [Conf]
  48. Michael A. Schuette, John Paul Shen
    On-Line Self-Monitoring Using Signatured Instruction Streams. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:275-282 [Conf]
  49. John Paul Shen, F. Joel Ferguson
    Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:475-484 [Conf]
  50. Kent D. Wilken, John Paul Shen
    Continuous Signature Monitoring: Efficient Concurrent-Detection of Processor Control Errors. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:914-925 [Conf]
  51. Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen
    Dynamic speculative precomputation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:306-317 [Conf]
  52. Mauricio Breternitz Jr., John Paul Shen
    Organization of array data for concurrent memory access. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:97-99 [Conf]
  53. Mauricio Breternitz Jr., John Paul Shen
    Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:114-123 [Conf]
  54. Yuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen
    PipeRench implementation of the instruction path coprocessor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:147-158 [Conf]
  55. Trung A. Diep, John Paul Shen, Mike Phillip
    EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:225-235 [Conf]
  56. Andrew S. Huang, John Paul Shen
    A limit study of local memory requirements using value reuse profiles. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:71-81 [Conf]
  57. Richard A. Hankins, Trung A. Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John Paul Shen
    Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:151-164 [Conf]
  58. Derek B. Noonburg, John Paul Shen
    Theoretical modeling of superscalar processor performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:52-62 [Conf]
  59. Mikko H. Lipasti, John Paul Shen
    Exceeding the Dataflow Limit via Value Prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:226-237 [Conf]
  60. Michael A. Schuette, John Paul Shen
    An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:2-11 [Conf]
  61. Andrew Wolfe, John Paul Shen
    Flexible processors: a promising application-specific processor design approach. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:30-39 [Conf]
  62. Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Pat Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Shen, Clair Webb
    Die Stacking (3D) Microarchitecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:469-479 [Conf]
  63. Chris J. Newburn, John Paul Shen
    Compiler Support for Low-Cost Synchronization Among Threads. [Citation Graph (0, 0)][DBLP]
    PARCO, 1997, pp:485-494 [Conf]
  64. Shih-wei Liao, Perry H. Wang, Hong Wang, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery
    Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. [Citation Graph (0, 0)][DBLP]
    PLDI, 2002, pp:117-128 [Conf]
  65. Alexander G. Dean, John Paul Shen
    Techniques for Software Thread Integration in Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1998, pp:322-333 [Conf]
  66. Alexander G. Dean, John Paul Shen
    System-Level Issues for Software Thread Integration: Guest Triggering and Host Selection. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1999, pp:234- [Conf]
  67. Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen
    A framework for modeling and optimization of prescient instruction prefetch. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2003, pp:13-24 [Conf]
  68. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
    Superscalar Processor Validation at the Microarchitecture Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:300-305 [Conf]
  69. Bryan Black, John Paul Shen
    Calibration of Microprocessor Performance Models. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:5, pp:59-65 [Journal]
  70. Trung A. Diep, John Paul Shen
    VMW: A Visualization-Based Microarchitecture Workbench. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1995, v:28, n:12, pp:57-64 [Journal]
  71. Mikko H. Lipasti, John Paul Shen
    Superspeculative Microarchitecture for Beyond AD 2000. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:9, pp:59-66 [Journal]
  72. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
    Effectiveness of Microarchitecture Test Program Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:38-49 [Journal]
  73. Mikko H. Lipasti, John Paul Shen
    Exploiting Value Locality to Exceed the Dataflow Limit. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1998, v:26, n:4, pp:505-538 [Journal]
  74. Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
    Helper Threads via Virtual Multithreading. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:6, pp:74-82 [Journal]
  75. John Paul Shen, John P. Hayes, Luigi Ciminiera, Angelo Serra
    Fault-tolerance and performance analysis of beta-networks. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1986, v:3, n:3, pp:231-249 [Journal]
  76. Ronald P. Bianchini Jr., John Paul Shen
    Interprocessor Traffic Scheduling Algorithm for Multiple-Processor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:4, pp:396-409 [Journal]
  77. Michael A. Schuette, John Paul Shen
    Processor Control Flow Monitoring Using Signatured Instruction Streams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:3, pp:264-276 [Journal]
  78. Michael A. Schuette, John Paul Shen
    Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:2, pp:129-140 [Journal]
  79. John Paul Shen, F. Joel Ferguson
    The Design of Easily Tastabel VLSI Array Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:6, pp:554-560 [Journal]
  80. John Paul Shen, John P. Hayes
    Fault-Tolerance of Dynamic-Full-Access Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:3, pp:241-248 [Journal]
  81. F. Joel Ferguson, John Paul Shen
    A CMOS fault extractor for inductive fault analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:11, pp:1181-1194 [Journal]
  82. Kent D. Wilken, John Paul Shen
    Continuous signature monitoring: low-cost concurrent detection of processor control errors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:6, pp:629-641 [Journal]

  83. Fault tolerance analysis of several interconnection networks. [Citation Graph (, )][DBLP]


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