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Huiyang Zhou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Huiyang Zhou, Thomas M. Conte
    Code Size Efficiency in Global Scheduling for ILP Processors. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2002, pp:79-90 [Conf]
  2. Huiyang Zhou
    Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:231-242 [Conf]
  3. Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
    Adaptive Mode Control: A Static-Power-Efficient Cache Design. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:61-0 [Conf]
  4. Jingfei Kong, Cliff Changchun Zou, Huiyang Zhou
    Improving software security via runtime instruction-level taint checking. [Citation Graph (0, 0)][DBLP]
    ASID, 2006, pp:18-24 [Conf]
  5. Huiyang Zhou, Thomas M. Conte
    Enhancing memory level parallelism via recovery-free value prediction. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:326-335 [Conf]
  6. Huiyang Zhou, Jill Flanagan, Thomas M. Conte
    Detecting Global Stride Locality in Value Streams. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:324-335 [Conf]
  7. Huiyang Zhou, Matthew D. Jennings, Thomas M. Conte
    Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:223-238 [Conf]
  8. Yi Ma, Hongliang Gao, Huiyang Zhou
    Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:8, pp:1057-1061 [Journal]
  9. Huiyang Zhou, Thomas M. Conte
    Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:897-912 [Journal]
  10. Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
    Adaptive mode control: A static-power-efficient cache design. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:3, pp:347-372 [Journal]
  11. Yi Ma, Hongliang Gao, Martin Dimitrov, Huiyang Zhou
    Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1080-1093 [Journal]

  12. Unified Architectural Support for Soft-Error Protection or Software Bug Detection. [Citation Graph (, )][DBLP]

  13. Understanding software approaches for GPGPU reliability. [Citation Graph (, )][DBLP]

  14. Anomaly-based bug prediction, isolation, and validation: an automated approach for software debugging. [Citation Graph (, )][DBLP]

  15. Accelerating MATLAB Image Processing Toolbox functions on GPUs. [Citation Graph (, )][DBLP]

  16. Deconstructing new cache designs for thwarting software cache-based side channel attacks. [Citation Graph (, )][DBLP]

  17. Address-branch correlation: A novel locality for long-latency hard-to-predict branches. [Citation Graph (, )][DBLP]

  18. Hardware-software integrated approaches to defend against software cache-based side channel attacks. [Citation Graph (, )][DBLP]

  19. Efficient Transient-Fault Tolerance for Multithreaded Processors using Dual-Thread Execution. [Citation Graph (, )][DBLP]

  20. A GPGPU compiler for memory optimization and parallelism management. [Citation Graph (, )][DBLP]

  21. An optimizing compiler for GPGPU programs with input-data sharing. [Citation Graph (, )][DBLP]

  22. A case for fault tolerance and performance enhancement using chip multi-processors. [Citation Graph (, )][DBLP]

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