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Thomas M. Conte: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Huiyang Zhou, Thomas M. Conte
    Code Size Efficiency in Global Scheduling for ILP Processors. [Citation Graph (0, 0)][DBLP]
    Interaction between Compilers and Computer Architectures, 2002, pp:79-90 [Conf]
  2. Kim M. Hazelwood, Thomas M. Conte
    A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2000, pp:71-80 [Conf]
  3. Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte
    Path Prediction for High Issue-Rate Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:178-188 [Conf]
  4. Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte
    A Fast Interrupt Handling Scheme for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:136-141 [Conf]
  5. Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
    Adaptive Mode Control: A Static-Power-Efficient Cache Design. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:61-0 [Conf]
  6. Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte
    Value Speculation Scheduling for High Performance Processors. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1998, pp:262-271 [Conf]
  7. Sanjeev Banerjia, William A. Havanki, Thomas M. Conte
    Treegion Scheduling for Highly Parallel Processors. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:1074-1078 [Conf]
  8. Mouna Nakkar, David G. Bentlage, John Harding, David Schwartz, Paul D. Franzon, Thomas M. Conte
    Dynamically Programmable Cache Evaluation and Virtualization. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:246- [Conf]
  9. Thomas M. Conte, Charles E. Gimarc
    Fast Simulation of Computer Architectures: Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:184- [Conf]
  10. Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye
    A technique to determine power-efficient, high-performance superscalar processors. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:324-333 [Conf]
  11. Thomas M. Conte, Andrew Wolfe
    Combining General-Purpose and Multimedia in One Package: Challenges and Opportunities. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1997, pp:708-712 [Conf]
  12. J. Stan Cox, David P. Howell, Thomas M. Conte
    Commercializing profile-driven optimization. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:221-228 [Conf]
  13. Emre Özer, Thomas M. Conte, Saurabh Sharma
    Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. [Citation Graph (0, 0)][DBLP]
    HiPC, 2001, pp:192-203 [Conf]
  14. William A. Havanki, Sanjeev Banerjia, Thomas M. Conte
    Treegion Scheduling for Wide Issue Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:266-276 [Conf]
  15. Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes
    Reducing State Loss For Effective Trace Sampling of Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:468-477 [Conf]
  16. Thomas M. Conte, William H. Mangione-Smith
    Determining Cost-Effective Multiple Issue Processor Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:94-101 [Conf]
  17. Huiyang Zhou, Thomas M. Conte
    Enhancing memory level parallelism via recovery-free value prediction. [Citation Graph (0, 0)][DBLP]
    ICS, 2003, pp:326-335 [Conf]
  18. Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel
    Optimization of Instruction Fetch Mechanisms for High Issue Rates. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:333-344 [Conf]
  19. Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang
    Comparing Software and Hardware Schemes For Reducing the Cost of Branches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:224-233 [Conf]
  20. Huiyang Zhou, Jill Flanagan, Thomas M. Conte
    Detecting Global Stride Locality in Value Streams. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:324-335 [Conf]
  21. Huiyang Zhou, Matthew D. Jennings, Thomas M. Conte
    Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:223-238 [Conf]
  22. Thomas M. Conte
    Tradeoffs in processor/memory interfaces for superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:202-205 [Conf]
  23. Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye
    Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:201-211 [Conf]
  24. Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch
    Accurate and Practical Profile-driven Compilation Using the Profile Buffer. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:36-45 [Conf]
  25. Thomas M. Conte, Burzin A. Patel, J. Stan Cox
    Using branch handling hardware to support profile-driven optimization. [Citation Graph (0, 0)][DBLP]
    MICRO, 1994, pp:12-21 [Conf]
  26. Thomas M. Conte, Sumedh W. Sathaye
    Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:208-218 [Conf]
  27. Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia
    A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1996, pp:4-13 [Conf]
  28. Sergei Y. Larin, Thomas M. Conte
    Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:82-92 [Conf]
  29. Emre Özer, Sanjeev Banerjia, Thomas M. Conte
    Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:308-315 [Conf]
  30. Wen-mei W. Hwu, Thomas M. Conte
    A Simulation Study of Simultaneous Vector Prefetch Performance in Multiprocessor Memory Subsystems (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1989, pp:227- [Conf]
  31. Thomas M. Conte, Wen-mei W. Hwu
    Advances in Benchmarking Techniques: New Standards and Quantitative Metrics. [Citation Graph (0, 0)][DBLP]
    Advances in Computers, 1995, v:41, n:, pp:231-253 [Journal]
  32. Pradip Bose, Thomas M. Conte
    Performance Analysis and Its Impact on Design. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1998, v:31, n:5, pp:41-49 [Journal]
  33. Thomas M. Conte
    Choosing the Brain(s) of an Embedded System. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:7, pp:106-107 [Journal]
  34. Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe
    Challenges to Combining General-Purpose and Multimedia Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:33-37 [Journal]
  35. Thomas M. Conte, Wen-mei W. Hwu
    Benchmark Characterization. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:1, pp:48-56 [Journal]
  36. Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson
    Compilers for Instruction-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:63-69 [Journal]
  37. Thomas M. Conte
    Importance of Profiling and Compatibility. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1996, v:28, n:4es, pp:26- [Journal]
  38. Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman
    Editor's Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:5, pp:325-326 [Journal]
  39. Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman
    Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:6, pp:425-426 [Journal]
  40. Alessio Bechini, Thomas M. Conte, Cosimo Antonio Prete
    Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:4, pp:8-9 [Journal]
  41. Monther Aldwairi, Thomas M. Conte, Paul D. Franzon
    Configurable string matching hardware for speeding up intrusion detection. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:99-107 [Journal]
  42. Saurabh Sharma, Jesse G. Beu, Thomas M. Conte
    Spectral prefetcher: An effective mechanism for L2 cache prefetching. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:4, pp:423-450 [Journal]
  43. Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte
    MPS: Miss-Path Scheduling for Multiple-Issue Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:12, pp:1382-1397 [Journal]
  44. William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu
    The Effect of Code Expanding Optimizations on Instruction Cache Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1045-1057 [Journal]
  45. Thomas M. Conte, Mary Ann Hirsch, Wen-mei W. Hwu
    Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:6, pp:714-720 [Journal]
  46. Thomas M. Conte, Sumedh W. Sathaye
    Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:8, pp:814-825 [Journal]
  47. Chao-ying Fu, Jill T. Bodine, Thomas M. Conte
    Modeling Value Speculation: An Optimal Edge Selection Problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:3, pp:277-292 [Journal]
  48. Wen-mei W. Hwu, Thomas M. Conte
    The Susceptibility of Programs to Context Switching. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:9, pp:994-1003 [Journal]
  49. Huiyang Zhou, Thomas M. Conte
    Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:897-912 [Journal]
  50. Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte
    Adaptive mode control: A static-power-efficient cache design. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:3, pp:347-372 [Journal]
  51. Emre Özer, Thomas M. Conte
    High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:12, pp:1132-1142 [Journal]
  52. Thomas M. Conte
    Keynote: Insight, Not (Random) Numbers: An Embedded Perspective. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:3- [Conf]
  53. Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen
    System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:129-137 [Journal]

  54. Combining cluster sampling with single pass methods for efficient sampling regimen design. [Citation Graph (, )][DBLP]


  55. Energy-aware opcode design. [Citation Graph (, )][DBLP]


  56. A Power Model for Register-Sharing Structures. [Citation Graph (, )][DBLP]


  57. Insight, not (random) numbers. [Citation Graph (, )][DBLP]


  58. Reverse State Reconstruction for Sampled Microarchitectural Simulation. [Citation Graph (, )][DBLP]


  59. On power and energy trends of IEEE 802.11n PHY. [Citation Graph (, )][DBLP]


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