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Sudhakar Yalamanchili: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Eileen Tien Lin, Edward Omiecinski, Sudhakar Yalamanchili
    Large Join Optimization on a Hypercube Multiprocessor. [Citation Graph (2, 17)][DBLP]
    IEEE Trans. Knowl. Data Eng., 1994, v:6, n:2, pp:304-315 [Journal]
  2. Sudhakar Yalamanchili, Miroslaw Malek, Jake K. Aggarwal
    Workstations in a Local Area Network Environment. [Citation Graph (1, 0)][DBLP]
    IEEE Computer, 1984, v:17, n:11, pp:74-86 [Journal]
  3. Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
    A new switch scheduling algorithm to improve QoS in the multimedia router. [Citation Graph (0, 0)][DBLP]
    IEEE Workshop on Multimedia Signal Processing, 2002, pp:376-379 [Conf]
  4. Subramanian Ramaswamy, Sudhakar Yalamanchili
    Customized Placement for High Performance Embedded Processor Caches. [Citation Graph (0, 0)][DBLP]
    ARCS, 2007, pp:69-82 [Conf]
  5. Krishna V. Palem, Lakshmi N. Chakrapani, Sudhakar Yalamanchili
    A Framework for Compiler Driven Design Space Exploration for Embedded System Customization. [Citation Graph (0, 0)][DBLP]
    ASIAN, 2004, pp:395-406 [Conf]
  6. Blanca Caminero, Francisco J. Quiles, José Duato, Damon S. Love, Sudhakar Yalamanchili
    Performance Evaluation of the Multimedia Router with MPEG-2 Video Traffic. [Citation Graph (0, 0)][DBLP]
    CANPC, 1999, pp:62-76 [Conf]
  7. Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West
    ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:115-124 [Conf]
  8. Eileen Tien Lin, Edward Omiecinski, Sudhakar Yalamanchili
    Parallel Optimization and Execution of Large Join Queries. [Citation Graph (0, 0)][DBLP]
    FGCS, 1992, pp:907-914 [Conf]
  9. Richard West, Raj Krishnamurthy, W. K. Norton, Karsten Schwan, Sudhakar Yalamanchili, Marcel-Catalin Rosu, V. Sarat
    QUIC: A Quality of Service Network Interface Layer for Communication in NOWs. [Citation Graph (0, 0)][DBLP]
    Heterogeneous Computing Workshop, 1999, pp:199-208 [Conf]
  10. Indrani Paul, Sudhakar Yalamanchili, José Duato
    Algorithms for Switch-Scheduling in the Multimedia Router for LANs. [Citation Graph (0, 0)][DBLP]
    HiPC, 2002, pp:219-231 [Conf]
  11. Sudhakar Yalamanchili
    The Customization Landscape for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    HiPC, 2002, pp:693-696 [Conf]
  12. Binh Vien Dao, Sudhakar Yalamanchili, José Duato
    Architectural Support for Reducing Communication Overhead in Multiprocessor Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 1997, pp:343-352 [Conf]
  13. José Duato, Sudhakar Yalamanchili, Blanca Caminero, Damon S. Love, Francisco J. Quiles
    MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:300-309 [Conf]
  14. Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel
    Power Constrained Design of Multiprocessor Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:408-416 [Conf]
  15. Sudhakar Yalamanchili, Jake K. Aggarwal
    Algebraic Properties of some Parallel Processor Interconnection Networks. [Citation Graph (0, 7)][DBLP]
    ICDE, 1984, pp:611-618 [Conf]
  16. Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
    A Cost-Effective Hardware Link Scheduling Algorithm for the Multimedia Router (MMR). [Citation Graph (0, 0)][DBLP]
    ICN (2), 2001, pp:358-369 [Conf]
  17. José Duato, V. B. Dao, Patrick T. Gaughan, Sudhakar Yalamanchili
    Scouting: Fully Adaptive, Deadlock-Free Routing in Faulty Pipelined Networks. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:608-613 [Conf]
  18. José Duato, Pedro López, Federico Silla, Sudhakar Yalamanchili
    A High Performance Router Architecture for Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    ICPP, Vol. 1, 1996, pp:61-68 [Conf]
  19. Young-Joo Suh, Binh Vien Dao, José Duato, Sudhakar Yalamanchili
    Software Based Fault-Tolerant Oblivious Routing in Pipelined Networks. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1995, pp:101-105 [Conf]
  20. Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
    Tuning Buffer Size in the Multimedia Router (MMR). [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:160- [Conf]
  21. Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
    Investigating Switch Scheduling Algorithms to Support QoS in the Multimedia Router. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  22. Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
    A Solution for Handling Hybrid Traffic in Clustered Environments: The MultiMedia Router MMR. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:197- [Conf]
  23. José Duato, Pedro López, Sudhakar Yalamanchili
    Deadlock- and Livelock-Free Routing Protocols for Wave Switching. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:570-577 [Conf]
  24. Patrick T. Gaughan, Sudhakar Yalamanchili
    Analytical Models of Bandwidth Allocation in Pipelined k-ary n-cubes. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:395-400 [Conf]
  25. Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West
    Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:30- [Conf]
  26. Damon S. Love, Sudhakar Yalamanchili, José Duato, Blanca Caminero, Francisco J. Quiles
    Switch Scheduling in the Multimedia Router (MMR). [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:5-12 [Conf]
  27. Ajay Mohindra, Sudhakar Yalamanchili
    Dominant Representations: A Paradigm for Mapping Parallel Computations. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:67-71 [Conf]
  28. Hatem Sellami, Sudhakar Yalamanchili
    Time scale combining of conservative parallel discrete event simulations. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:599-0 [Conf]
  29. Young-Joo Suh, Sudhakar Yalamanchili
    Algorithms for All-to-All Personalized Exchange in 2D and 3D Tori. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:808-814 [Conf]
  30. James D. Allen, Patrick T. Gaughan, David E. Schimmel, Sudhakar Yalamanchili
    Ariadne - An Adaptive Router for Fault-Tolerant Multicomputers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:278-288 [Conf]
  31. Binh Vien Dao, José Duato, Sudhakar Yalamanchili
    Configurable Flow Control Mechanisms for Fault-Tolerant Routing. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:220-229 [Conf]
  32. Hatem Sellami, James D. Allen, David E. Schimmel, Sudhakar Yalamanchili
    Simulation of Marked Graphs on SIMD Architectures Using Efficient Memory Management. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 1994, pp:343-348 [Conf]
  33. Tsai Chi Huang, Sudhakar Yalamanchili, Roy W. Melton, Philip R. Bingham, Cecil O. Alford
    Teaching Pipelining and Concurrency using Hardware Description Languages. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:55-56 [Conf]
  34. Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel
    Power/Performance Trade-offs for Direct Networks. [Citation Graph (0, 0)][DBLP]
    PCRCW, 1997, pp:231-246 [Conf]
  35. Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
    A Hardware Approach to QoS Support in Cluster Environments: The Multimedia Router MMR. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:220-226 [Conf]
  36. Craig Ulmer, Sudhakar Yalamanchili
    An Extensible Message Layer for High-Performance Clusters. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  37. Craig Ulmer, Sudhakar Yalamanchili
    A Tunable Communications Library for Data Injection. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:1630-1636 [Conf]
  38. Daniela Rosu, Karsten Schwan, Sudhakar Yalamanchili
    FARA - A Framework for Adaptive Resource Allocation in Complex Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 1998, pp:79-84 [Conf]
  39. Daniela Rosu, Karsten Schwan, Sudhakar Yalamanchili, Rakesh Jha
    On adaptive resource allocation for complex real-time application. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1997, pp:320-329 [Conf]
  40. Patrick T. Gaughan, Sudhakar Yalamanchili
    Pipelined Circuit-Switching: A Fault-Tolerant Variant of Wormhole Routing. [Citation Graph (0, 0)][DBLP]
    SPDP, 1992, pp:148-155 [Conf]
  41. Hatem Sellami, Sudhakar Yalamanchili
    Partitioning and Mapping a Class of Parallel Multiprocessor Simulation Models. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:360-367 [Conf]
  42. Sudhakar Yalamanchili, Lynn E. Te Winkel, David L. Perschbacher, Belle Shenoy
    Genie: An Environment for Partitioning and Mapping in Embedded Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:522-529 [Conf]
  43. Patrick T. Gaughan, Sudhakar Yalamanchili
    Adaptive Routing Protocols for Hypercube Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1993, v:26, n:5, pp:12-23 [Journal]
  44. Sudhakar Yalamanchili, Jake K. Aggarwal
    Reconfiguration Strategies for Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1985, v:18, n:12, pp:44-61 [Journal]
  45. Christopher H. de Castro, Sudhakar Yalamanchili
    Partitioning Coarse-Grain Signal Flow Graphs for Heterogeneous DSP Architectures. [Citation Graph (0, 0)][DBLP]
    Int. Journal in Computer Simulation, 1994, v:4, n:4, pp:0-0 [Journal]
  46. Sudhakar Yalamanchili, Todd Carpenter
    Paradigms for Modeling and Simulation of Multiprocessor Architectures. [Citation Graph (0, 0)][DBLP]
    Int. Journal in Computer Simulation, 1996, v:6, n:1, pp:137-0 [Journal]
  47. Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
    MMR: A MultiMedia Router architecture to support hybrid workloads. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2006, v:66, n:2, pp:307-321 [Journal]
  48. S. Y. Lee, Sudhakar Yalamanchili, Jake K. Aggarwal
    Parallel image normalization on a mesh connected array processor. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1987, v:20, n:1, pp:115-124 [Journal]
  49. Sudhakar Yalamanchili, Jake K. Aggarwal
    Analysis of a model for parallel image processing. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1985, v:18, n:1, pp:1-16 [Journal]
  50. Sudhakar Yalamanchili, Jake K. Aggarwal
    A system organization for parallel image processing. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1985, v:18, n:1, pp:17-29 [Journal]
  51. Patrick T. Gaughan, Binh Vien Dao, Sudhakar Yalamanchili, David E. Schimmel
    Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:6, pp:651-665 [Journal]
  52. Patrick T. Gaughan, Sudhakar Yalamanchili
    A Performance Model of Pipelined K-ary n-cubes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:8, pp:1059-1063 [Journal]
  53. Hari Lalgudi, Ian F. Akyildiz, Sudhakar Yalamanchili
    Augmented Binary Hypercube: A New Architecture for Processor Management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:8, pp:980-984 [Journal]
  54. Sudhakar Yalamanchili, Jake K. Aggarwal
    A Characterization and Analysis of Parallel Processor Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:6, pp:680-691 [Journal]
  55. Hatem Sellami, Sudhakar Yalamanchili
    Parallelism in Sequential Multiprocessor Simulation Models: A Case Study. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Model. Comput. Simul., 1995, v:5, n:2, pp:101-128 [Journal]
  56. Blanca Caminero, Carmen Carrión, Francisco J. Quiles, José Duato, Sudhakar Yalamanchili
    Traffic Scheduling Solutions with QoS Support for an Input-Buffered MultiMedia Router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:11, pp:1009-1021 [Journal]
  57. Binh Vien Dao, José Duato, Sudhakar Yalamanchili
    Dynamically Configurable Message Flow Control for Fault-Tolerant Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:1, pp:7-22 [Journal]
  58. Patrick T. Gaughan, Sudhakar Yalamanchili
    A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:5, pp:482-497 [Journal]
  59. Young-Joo Suh, Binh Vien Dao, José Duato, Sudhakar Yalamanchili
    Software-Based Rerouting for Fault-Tolerant Pipelined Communication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:3, pp:193-211 [Journal]
  60. Young-Joo Suh, Sudhakar Yalamanchili
    Configurable Algorithms for Complete Exchange in 2D Meshes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:4, pp:337-356 [Journal]
  61. Young-Joo Suh, Sudhakar Yalamanchili
    All-To-All Communication with Minimum Start-Up Costs in 2D/3D Tori and Meshes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:5, pp:442-458 [Journal]

  62. HyVM - Hybrid Virtual Machines - Efficient Use of Future Heterogeneous Chip Multiprocessors. [Citation Graph (, )][DBLP]


  63. Modeling GPU-CPU workloads and systems. [Citation Graph (, )][DBLP]


  64. ShareStreams-V: A Virtualized QoS Packet Scheduling Accelerator. [Citation Graph (, )][DBLP]


  65. An Utilization Driven Framework for Energy Efficient Caches. [Citation Graph (, )][DBLP]


  66. Architecture and Hardware for Scheduling Gigabit Packet Streams. [Citation Graph (, )][DBLP]


  67. Harmony: an execution model and runtime for heterogeneous many core systems. [Citation Graph (, )][DBLP]


  68. A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. [Citation Graph (, )][DBLP]


  69. Improving cache efficiency via resizing + remapping. [Citation Graph (, )][DBLP]


  70. Customizable Fault Tolerant Caches for Embedded Processors. [Citation Graph (, )][DBLP]


  71. An energy efficient cache design using spin torque transfer (STT) RAM. [Citation Graph (, )][DBLP]


  72. Adaptive routing in generalized hypercube architectures. [Citation Graph (, )][DBLP]


  73. A characterization and analysis of PTX kernels. [Citation Graph (, )][DBLP]


  74. Partitioning and mapping in embedded multiprocessor architectures in the presence of constraints. [Citation Graph (, )][DBLP]


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