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Publications of Author

1. A. Houelle, Habib Mehrez, N. Vaucher, Luis A. Montalvo, Alain Guyot
   Application of fast layout synthesis environment to dividers evaluation. [Citation Graph (0, 0)][DBLP]
   IEEE Symposium on Computer Arithmetic, 1995, pp:67-74 [Conf]
   
2. M. Aberbour, Habib Mehrez, François Durbin, Jacques Haussy, P. Lalande, André Tissot
   A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology. [Citation Graph (0, 0)][DBLP]
   CAMP, 2000, pp:155-162 [Conf]
   
3. Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
   A multilevel hierarchical interconnection structure for FPGA. [Citation Graph (0, 0)][DBLP]
   FPGA, 2006, pp:225- [Conf]
   
4. Zied Marrakchi, Hayder Mrabet, Habib Mehrez
   Configuration tools for a new multilevel hierarchical FPGA. [Citation Graph (0, 0)][DBLP]
   FPGA, 2006, pp:229- [Conf]
   
5. Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
   Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:675-679 [Conf]
   
6. Zied Marrakchi, Hayder Mrabet, Habib Mehrez
   A new Multilevel Hierarchical MFPGA and its suitable configuration tools. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2006, pp:263-268 [Conf]
   
7. Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot
   Implementation of Scalable Embedded FPGA for SOC. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2005, pp:59-62 [Conf]
   
8. Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot
   Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2006, pp:117-123 [Conf]
   
9. Alain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, N. Vaucher
   Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1995, pp:386-391 [Conf]
   
10. Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez
    Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:243-252 [Conf]
    
11. M. Aberbour, A. Houelle, Habib Mehrez, N. Vaucher, Alain Guyot
    On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:114-121 [Journal]
    
12. 
    Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). [Citation Graph (, )][DBLP]
    
    
13. 
    Efficient tree topology for FPGA interconnect network. [Citation Graph (, )][DBLP]
    
    
14. 
    Arithmetic Data Path Optimization Using Borrow-Save Representation. [Citation Graph (, )][DBLP]
    
    
15. 
    Application Specific FPGA Using Heterogeneous Logic Blocks. [Citation Graph (, )][DBLP]
    
    
16. 
    Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. [Citation Graph (, )][DBLP]
    
    
17. 
    The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. [Citation Graph (, )][DBLP]
    
    
18. 
    Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. [Citation Graph (, )][DBLP]