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Cesar Torres-Huitzil: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cesar Torres-Huitzil, Miguel Arias-Estrada
    An FPGA Architecture for High Speed Edge and Corner Detection. [Citation Graph (0, 0)][DBLP]
    CAMP, 2000, pp:112-116 [Conf]
  2. Santos López-Estrada, René Cumplido-Parra, Cesar Torres-Huitzil
    A Hybrid Approach for Target Detection Using CFAR Algorithm and Image Processing. [Citation Graph (0, 0)][DBLP]
    ENC, 2004, pp:108-115 [Conf]
  3. Bernard Girau, Cesar Torres-Huitzil
    FPGA implementation of an integrate-and-fire LEGION model for image segmentation. [Citation Graph (0, 0)][DBLP]
    ESANN, 2006, pp:173-178 [Conf]
  4. Cesar Torres-Huitzil, Miguel Arias-Estrada
    Configurable Hardware Architecture for Real-Time Window-Based Image Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1008-1011 [Conf]
  5. Cesar Torres-Huitzil, René Cumplido-Parra, Santos López-Estrada
    Design and Implementation of a CFAR Processor for Target Detection. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:943-947 [Conf]
  6. Cesar Torres-Huitzil, Bernard Girau
    FPGA Implementation of an Excitatory and Inhibitory Connectionist Model for Motion Perception. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:259-266 [Conf]
  7. Cesar Torres-Huitzil
    A Bit-Stream Pulse-Based Digital Neuron Model for Neural Networks. [Citation Graph (0, 0)][DBLP]
    ICONIP (3), 2006, pp:1150-1159 [Conf]
  8. Cesar Torres-Huitzil, Bernard Girau, Claudio Castellanos Sánchez
    On-chip visual perception of motion: A bio-inspired connectionist model on FPGA. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 2005, v:18, n:5-6, pp:557-565 [Journal]
  9. Cesar Torres-Huitzil, Miguel Arias-Estrada
    Real-time image processing with a compact FPGA-based systolic architecture. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 2004, v:10, n:3, pp:177-187 [Journal]
  10. Cesar Torres-Huitzil
    Area-Efficient Implementation of a Pulse-Mode Neuron Model. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  11. Cesar Torres-Huitzil, Bernard Girau, Adrien Gauffriau
    Hardware/Software Codesign for Embedded Implementation of Neural Networks. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:167-178 [Conf]
  12. Bernard Girau, Cesar Torres-Huitzil
    Massively distributed digital implementation of an integrate-and-fire LEGION network for visual scene segmentation. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2007, v:70, n:7-9, pp:1186-1197 [Journal]

  13. Implementation of Central Pattern Generator in an FPGA-Based Embedded System. [Citation Graph (, )][DBLP]


  14. Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity. [Citation Graph (, )][DBLP]


  15. Hardware Implementation of a CPG-Based Locomotion Control for Quadruped Robots. [Citation Graph (, )][DBLP]


  16. On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion. [Citation Graph (, )][DBLP]


  17. Fast Implementation of a Bio-inspired Model for Decentralized Gathering. [Citation Graph (, )][DBLP]


  18. Flexible Architecture for Three Classes of Optical Flow Extraction Algorithms. [Citation Graph (, )][DBLP]


  19. Embedded Harmonic Control for Trajectory Planning in Large Environments. [Citation Graph (, )][DBLP]


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