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Publications of Author

1. Cesar Torres-Huitzil, Miguel Arias-Estrada
   An FPGA Architecture for High Speed Edge and Corner Detection. [Citation Graph (0, 0)][DBLP]
   CAMP, 2000, pp:112-116 [Conf]
   
2. Alicia Morales-Reyes, Miguel Arias-Estrada
   Stereo Analysis Extension Based on BRDF Reciprocity. [Citation Graph (0, 0)][DBLP]
   CONIELECOMP, 2006, pp:53- [Conf]
   
3. Liz Castillo-Jimenez, Miguel Arias-Estrada
   Super-resolution with integrated radial distortion correction. [Citation Graph (0, 0)][DBLP]
   ENC, 2005, pp:165-173 [Conf]
   
4. Gerardo Sosa-Ramirez, Miguel Arias-Estrada
   3D Recovery with Free Hand Camera Motion. [Citation Graph (0, 0)][DBLP]
   ENC, 2005, pp:145-151 [Conf]
   
5. A. Lecerf, F. Vachon, D. Ouellet, Miguel Arias-Estrada
   FPGA Based Computer Vision Camera. [Citation Graph (0, 0)][DBLP]
   FPGA, 1999, pp:248- [Conf]
   
6. Miguel Arias-Estrada, Eduardo Rodríguez-Palacios
   An FPGA Co-processor for Real-Time Visual Tracking. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:710-719 [Conf]
   
7. Miguel Arias-Estrada, Juan M. Xicotencatl
   Multiple Stereo Matching Using an Extended Architecture. [Citation Graph (0, 0)][DBLP]
   FPL, 2001, pp:203-212 [Conf]
   
8. Selene Maya-Rueda, Miguel Arias-Estrada
   FPGA Processor for Real-Time Optical Flow Computation. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:1103-1106 [Conf]
   
9. Selene Maya, Rocio Reynoso, César Torres, Miguel Arias-Estrada
   Compact Spiking Neural Network Implementation in FPGA. [Citation Graph (0, 0)][DBLP]
   FPL, 2000, pp:270-276 [Conf]
   
10. Cesar Torres-Huitzil, Miguel Arias-Estrada
    Configurable Hardware Architecture for Real-Time Window-Based Image Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1008-1011 [Conf]
    
11. Juan M. Xicotencatl, Miguel Arias-Estrada
    FPGA Based High Density Spiking Neural Network Array. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1053-1056 [Conf]
    
12. J. J. Vega, M. R. Reynoso, Miguel Arias-Estrada, Leopoldo Altamirano Robles
    Bragg Curve Identification Using a Neural Network. [Citation Graph (0, 0)][DBLP]
    IJCNN (4), 2000, pp:379-382 [Conf]
    
13. Rafael Lemuz-López, Miguel Arias-Estrada
    Iterative Closest SIFT Formulation for Robust Feature Matching. [Citation Graph (0, 0)][DBLP]
    ISVC (2), 2006, pp:502-513 [Conf]
    
14. Rafael Lemuz-López, Miguel Arias-Estrada
    A Domain Reduction Algorithm for Incremental Projective Reconstruction. [Citation Graph (0, 0)][DBLP]
    ISVC (2), 2006, pp:564-575 [Conf]
    
15. Griselda Saldaña, Miguel Arias-Estrada
    Compact FPGA-based systolic array architecture suitable for vision systems. [Citation Graph (0, 0)][DBLP]
    ITNG, 2007, pp:1008-1013 [Conf]
    
16. Cesar Torres-Huitzil, Miguel Arias-Estrada
    Real-time image processing with a compact FPGA-based systolic architecture. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 2004, v:10, n:3, pp:177-187 [Journal]
    
17. 
    Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity. [Citation Graph (, )][DBLP]
    
    
18. 
    Ranking Corner Points by the Angular Difference between Dominant Edges. [Citation Graph (, )][DBLP]
    
    
19. 
    Hardware/Software FPGA Architecture for Robotics Applications. [Citation Graph (, )][DBLP]
    
    
20. 
    Creation of a 3D Robot Model and its Integration to a Microsoft Robotics Studio Simulation. [Citation Graph (, )][DBLP]
    
    
21. 
    Parallel Processor for 3D Recovery from Optical Flow. [Citation Graph (, )][DBLP]