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Didier Demigny: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Didier Demigny, Lounis Kessal, R. Bourguiba, N. Boudouani
    How to Use High Speed Reconfigurable FPGA for Real Time Image Processing? [Citation Graph (0, 0)][DBLP]
    CAMP, 2000, pp:240-0 [Conf]
  2. Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert, Gaston Cambon, Didier Demigny
    A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:722-732 [Conf]
  3. Nicolas Abel, Lounis Kessal, Didier Demigny
    Design flexibility using fpga dynamical reconfiguration. [Citation Graph (0, 0)][DBLP]
    ICIP, 2004, pp:2821-2824 [Conf]
  4. Didier Demigny
    Extension of Canny's Discrete Criteria to Second Derivative Filters Towards a Unified Approach. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 1998, pp:520-524 [Conf]
  5. Didier Demigny, F. G. Lorca, Lounis Kessal
    Evaluation of edge detectors performances with a discrete expression of Canny's criteria. [Citation Graph (0, 0)][DBLP]
    ICIP, 1995, pp:2169-2172 [Conf]
  6. Lounis Kessal, Didier Demigny, N. Boudouani, R. Bourgiba
    Reconfigurable Hardware for Real Time Image Processing. [Citation Graph (0, 0)][DBLP]
    ICIP, 2000, pp:- [Conf]
  7. F. G. Lorca, Lounis Kessal, Didier Demigny
    Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge Detection. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 1997, pp:406-409 [Conf]
  8. Didier Demigny, Lounis Kessal, J. Pons
    Fast Recursive Implementation of the Gaussian Filter. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:39-49 [Conf]
  9. P. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, M. Karabernou
    Two ASIC for Low and Middle Levels of Real Time Image Processing. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:3-14 [Conf]
  10. Lounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, M. Karabernou
    Reconfigurable Architecture Using High Speed FPGA. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:75-86 [Conf]
  11. Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon
    Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:176- [Conf]
  12. Nicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny
    Clear Stream towards Dynamically Reconfigurable Systems on Chip. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:98-104 [Conf]
  13. Pascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon
    Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:128-137 [Conf]
  14. Didier Demigny, Tawfik Kamlé
    A Discrete Expression of Canny's Criteria for Step Edge Detector Performances Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Pattern Anal. Mach. Intell., 1997, v:19, n:11, pp:1199-1211 [Journal]
  15. Lounis Kessal, Nicolas Abel, Didier Demigny
    Real-time image processing with dynamically reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 2003, v:9, n:5, pp:297-313 [Journal]
  16. Didier Demigny
    On optimal linear filtering for edge detection. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Image Processing, 2002, v:11, n:7, pp:728-737 [Journal]

  17. Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems. [Citation Graph (, )][DBLP]


  18. A reconfigurable FIR/FFT unit for wireless telecommunication systems. [Citation Graph (, )][DBLP]


  19. A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip. [Citation Graph (, )][DBLP]


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