The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Khaled Benkrid: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Arjun K. Pai, Khaled Benkrid, Danny Crookes
    Embedded Reconfigurable DCT Architectures Using Adder-Based Distributed Arithmetic. [Citation Graph (0, 0)][DBLP]
    CAMP, 2005, pp:81-86 [Conf]
  2. S. Belkacemi, Khaled Benkrid, Danny Crookes
    A Logic Based Hardware Development Environment. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:280-281 [Conf]
  3. Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
    Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:162-172 [Conf]
  4. Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
    A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:273-275 [Conf]
  5. Khaled Benkrid, S. Belkacemi
    An integrated framework for the high level design of high performance signal processing circuits on FPGAs (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:278- [Conf]
  6. Khaled Benkrid, S. Belkacemi, Danny Crookes
    A logic based approach to hardware abstraction. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:238- [Conf]
  7. Abdsamad Benkrid, Danny Crookes, Khaled Benkrid
    Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:238- [Conf]
  8. Khaled Benkrid, S. Sukhsawas, Danny Crookes, S. Belkacemi
    A single-FPGA implementation of image connected component labelling. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:238- [Conf]
  9. Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
    Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:553-564 [Conf]
  10. Khaled Benkrid, Danny Crookes, Abdsamad Benkrid, S. Belkacemi
    A Prolog-Based Hardware Development Environment. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:370-380 [Conf]
  11. Khaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid
    An FPGA-Based Image Connected Component Labeller. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1012-1015 [Conf]
  12. Khaled Benkrid, Danny Crookes, Abdsamad Benkrid
    Design and implementation of a novel algorithm for general purpose median filtering on FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:425-428 [Conf]
  13. Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
    Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:222-225 [Conf]
  14. S. Sukhsawas, Khaled Benkrid
    A High-Level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:229-232 [Conf]
  15. Khaled Benkrid, Abdsamad Benkrid, S. Belkacemi
    Efficient FPGA hardware development: A multi-language approach. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:4, pp:184-209 [Journal]
  16. Khaled Benkrid, Danny Crookes, Abdsamad Benkrid
    Towards a general framework for FPGA based image processing using hardware skeletons. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2002, v:28, n:7-8, pp:1141-1154 [Journal]
  17. Khaled Benkrid, Danny Crookes
    From application descriptions to hardware in seconds: a logic-based approach to bridging the gap. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:420-436 [Journal]
  18. Abdsamad Benkrid, Khaled Benkrid
    Handling finite length signals borders in two-channel multirate filter banks for perfect reconstruction. [Citation Graph (0, 0)][DBLP]
    Signal Processing, 2006, v:86, n:2, pp:375-387 [Journal]
  19. Khaled Benkrid, S. Belkacemi, Abdsamad Benkrid
    HIDE: A hardware intelligent description environment. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:283-300 [Journal]

  20. High performance FPGA-based core for BLAST sequence alignment with the two-hit method. [Citation Graph (, )][DBLP]


  21. Power Efficient Domain-Specific Reconfigurable Architectures for System-on-Chip Applications. [Citation Graph (, )][DBLP]


  22. Multi-Criteria Optimization and Performance Measurement of Domain-Specific Reconfigurable Architectures Targeting Image and Video Processing Applications. [Citation Graph (, )][DBLP]


  23. Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence Alignment. [Citation Graph (, )][DBLP]


  24. A high performance fpga-based implementation of position specific iterated blast. [Citation Graph (, )][DBLP]


  25. A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs. [Citation Graph (, )][DBLP]


  26. High Performance Biosequence Database Scanning using FPGAs. [Citation Graph (, )][DBLP]


  27. High Performance Monte-Carlo Based Option Pricing on FPGAs. [Citation Graph (, )][DBLP]


  28. HIDE+: A Logic Based Hardware Development Environment. [Citation Graph (, )][DBLP]


  29. Design and Implementation of an FPGA-based Core for Gapped BLAST Sequence Alignment with the Two-Hit Method. [Citation Graph (, )][DBLP]


Search in 0.005secs, Finished in 0.007secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002