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Monica Chawathe: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins
Compiling and Optimizing Image Processing Algorithms for FPGAs. [Citation Graph (0, 0)][DBLP]
CAMP, 2000, pp:222-231 [Conf] - A. P. Wim Böhm, J. Ross Beveridge, Bruce A. Draper, Charlie Ross, Monica Chawathe, Walid A. Najjar
Compiling ATR Probing Codes for Execution on FPGA Hardware. [Citation Graph (0, 0)][DBLP]
FCCM, 2002, pp:301-302 [Conf] - Bruce A. Draper, J. Ross Beveridge, A. P. Wim Böhm, Charles Ross, Monica Chawathe
Implementing Image Applications on FPGAs. [Citation Graph (0, 0)][DBLP]
ICPR (3), 2002, pp:265-268 [Conf] - Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hammes, Walid A. Najjar, J. Ross Beveridge, Charlie Ross, Monica Chawathe, Mitesh Desai, José Bins
Compiling SA-C Programs to FPGAs: Performance Results. [Citation Graph (0, 0)][DBLP]
ICVS, 2001, pp:220-235 [Conf] - Jeffrey Hammes, A. P. Wim Böhm, Charlie Ross, Monica Chawathe, Bruce A. Draper, Robert Rinker, Walid A. Najjar
Loop fusion and temporal common subexpression elimination in window-based loops. [Citation Graph (0, 0)][DBLP]
IPDPS, 2001, pp:142- [Conf] - Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper, Jeffrey Hammes, Robert Rinker, J. Ross Beveridge, Monica Chawathe, Charles Ross
High-Level Language Abstraction for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
IEEE Computer, 2003, v:36, n:8, pp:63-69 [Journal] - Bruce A. Draper, J. Ross Beveridge, A. P. Wim Böhm, Charles Ross, Monica Chawathe
Accelerated image processing on FPGAs. [Citation Graph (0, 0)][DBLP]
IEEE Transactions on Image Processing, 2003, v:12, n:12, pp:1543-1551 [Journal] - A. P. Wim Böhm, Jeffrey Hammes, Bruce A. Draper, Monica Chawathe, Charlie Ross, Robert Rinker, Walid A. Najjar
Mapping a Single Assignment Programming Language to Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
The Journal of Supercomputing, 2002, v:21, n:2, pp:117-130 [Journal] - Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm
An automated process for compiling dataflow graphs into reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:130-139 [Journal]
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