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Michel Paindavoine: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dominique Ginhac, Eri Prasetyo, Michel Paindavoine, Barthélémy Heyrman
    Principles of a CMOS Sensor Dedicated to Face Tracking and Recognition. [Citation Graph (0, 0)][DBLP]
    CAMP, 2005, pp:33-38 [Conf]
  2. E. Drege, Fan Yang, Michel Paindavoine, Hervé Abdi
    Face recognition: pre-processing techniques for linear autoassociators. [Citation Graph (0, 0)][DBLP]
    ESANN, 1998, pp:383-388 [Conf]
  3. Fan Yang, Michel Paindavoine, Hervé Abdi
    A Pre-Processing Technique Based on the Wavelet Transform for Linear Autoassociators with Applications to Face Recognition. [Citation Graph (0, 0)][DBLP]
    ICANN, 1997, pp:925-930 [Conf]
  4. Cyril Berthaud, El-Bay Bourennane, Michel Paindavoine, Claude Milan
    Implementation of a Real Time Image Rotation using B-Spline Interpolation on FPGA's Board. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 1998, pp:995-999 [Conf]
  5. Sophie Bouchoux, El-Bay Bourennane, Michel Paindavoine
    Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA. [Citation Graph (0, 0)][DBLP]
    ICIP, 2004, pp:2841-2844 [Conf]
  6. Jocelyn Chanussot, Michel Paindavoine, Patrick Lambert
    Real Time Vector Median Like Filter FPGA Design and Application to Color Image Filtering. [Citation Graph (0, 0)][DBLP]
    ICIP (2), 1999, pp:414-418 [Conf]
  7. Sophie Bouchoux, El-Bay Bourennane, Johel Mitéran, Michel Paindavoine
    Implementation of JPEG2000 Arithmetic Decoder on a Dynamically Reconfigurable ATMEL FPGA. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:237-238 [Conf]
  8. Vincent Brost, Fan Yang, Michel Paindavoine
    Embedded System Prototyping Experience Using Multi-DSPs VHDL Model. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:201-206 [Conf]
  9. Jerome Dubois, Dominique Ginhac, Michel Paindavoine
    Design of a 10000 Frames/s CMOS Sensor with In Situ Image Processing. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:177-182 [Conf]
  10. Barthélémy Heyrman, Michel Paindavoine
    SystemC design of a smart camera. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2006, pp:189-193 [Conf]
  11. Fan Yang, Michel Paindavoine, Hervé Abdi, Dominique Arnoult
    Panoramic face mosaicing and recognition using multi-cameras. [Citation Graph (0, 0)][DBLP]
    SITIS, 2005, pp:22-27 [Conf]
  12. El-Bay Bourennane, Claude Milan, Michel Paindavoine, Sophie Bouchoux
    Real Time Image Rotation Using Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 2002, v:8, n:4, pp:277-289 [Journal]
  13. Barthélémy Heyrman, Michel Paindavoine, Renaud Schmit, Laurent Letellier, Thierry Collette
    Smart camera design for intensive embedded computing. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 2005, v:11, n:4, pp:282-289 [Journal]
  14. D. Rivero, Michel Paindavoine, S. Petit
    Real-time Sub-pixel Cross Bar Position Metrology. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 2002, v:8, n:2, pp:105-113 [Journal]
  15. Lionel Torres, El-Bay Bourennane, Michel Robert, Michel Paindavoine
    A Recursive Digital Filter Implementation for Noisy and Blurred Images. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1998, v:4, n:3, pp:181-191 [Journal]
  16. E. Bourennane, Pierre Gouton, Michel Paindavoine, Frédéric Truchetet
    Generalization of Canny-Deriche filter for detection of noisy exponential edge. [Citation Graph (0, 0)][DBLP]
    Signal Processing, 2002, v:82, n:10, pp:1317-1328 [Journal]
  17. Vincent Brost, Fan Yang, Michel Paindavoine
    A modular VLIW Processor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3968-3971 [Conf]
  18. Nicolas Farrugia, Franck Mamalet, Sébastien Roux, Fan Yang, Michel Paindavoine
    A Parallel Face Detection System Implemented on FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3704-3707 [Conf]

  19. Contactless Palmprint Recognition Using Gabor Filter. [Citation Graph (, )][DBLP]

  20. A 8 bits Pipeline Analog to Digital Converter Design for High Speed Camera Application [Citation Graph (, )][DBLP]

  21. Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6µm CMOS Process [Citation Graph (, )][DBLP]

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