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José L. Sánchez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Francisco José Alfaro, Aurelio Bermúdez, Rafael Casado, José Duato, Francisco J. Quiles, José L. Sánchez
    On the Performance of Up*/Down* Routing. [Citation Graph (0, 0)][DBLP]
    CANPC, 2000, pp:61-72 [Conf]
  2. Aurelio Bermúdez, Francisco José Alfaro, Rafael Casado, José Duato, Francisco J. Quiles, José L. Sánchez
    Extending Dynamic Reconfiguration to NOWs with Adaptive Routing. [Citation Graph (0, 0)][DBLP]
    CANPC, 2000, pp:73-83 [Conf]
  3. Rafael Casado, Francisco J. Quiles, José L. Sánchez, José Duato
    Deadlock-Free Routing in Irregular Networks with Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP]
    CANPC, 1999, pp:165-180 [Conf]
  4. Petra Povalej, Mateja Verlic, Peter Kokol, José L. Sánchez, Jose F. Sigut
    Identifying Lymphoma in Microscopy Images with Classificational Cellular Automata. [Citation Graph (0, 0)][DBLP]
    CBMS, 2006, pp:309-314 [Conf]
  5. Francisco José Alfaro, José L. Sánchez
    Tuning Buffer Size in InfiniBand to Guarantee QoS. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:873-881 [Conf]
  6. Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, Jose Flich, Francisco J. Quiles, José Duato
    Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2006, pp:884-895 [Conf]
  7. Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato
    Providing Full QoS Support in Clusters Using Only Two VCs at the Switches. [Citation Graph (0, 0)][DBLP]
    HiPC, 2005, pp:158-169 [Conf]
  8. Raúl Martínez, Francisco José Alfaro, José L. Sánchez
    Improving the Flexibility of the Deficit Table Scheduler. [Citation Graph (0, 0)][DBLP]
    HiPC, 2006, pp:84-97 [Conf]
  9. Rafael Casado, Aurelio Bermúdez, Francisco J. Quiles, José L. Sánchez, José Duato
    Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area Networks. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:85-96 [Conf]
  10. Alejandro Martínez, G. Apostolopoulos, Francisco José Alfaro, José L. Sánchez, José Duato
    QoS Support for Video Transmission in High-Speed Interconnects. [Citation Graph (0, 0)][DBLP]
    HPCC, 2006, pp:631-641 [Conf]
  11. Raúl Martínez, Francisco José Alfaro, José L. Sánchez
    Providing Quality of Service over Advanced Switching. [Citation Graph (0, 0)][DBLP]
    ICPADS (1), 2006, pp:223-234 [Conf]
  12. Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato
    Scalable Low-Cost QoS Support for Single-chip Switches. [Citation Graph (0, 0)][DBLP]
    ICPADS (1), 2006, pp:439-446 [Conf]
  13. Francisco José Alfaro, José L. Sánchez, José Duato
    A New Proposal to Fill in the InfiniBand Arbitration Tables. [Citation Graph (0, 0)][DBLP]
    ICPP, 2003, pp:133-0 [Conf]
  14. Raúl Martínez, Francisco José Alfaro, José L. Sánchez
    Decoupling the Bandwidth and Latency Bounding for Table-based Schedulers. [Citation Graph (0, 0)][DBLP]
    ICPP, 2006, pp:155-163 [Conf]
  15. Francisco José Alfaro, José L. Sánchez, José Duato
    A Strategy to Manage Time Sensitive Traffic in InfiniBand. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  16. Francisco José Alfaro, José L. Sánchez, José Duato, Chita R. Das
    A Strategy to Compute the InfiniBand Arbitration Tables. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  17. Pedro Javier García, M. D. Mora, Francisco José Alfaro, José L. Sánchez, Jose Flich
    Evaluation of Alternative Arbitration Policies for Myrinet Switches. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  18. José L. Sánchez, José M. García, Francisco José Alfaro
    Reconfigurable Wormhole Networks: A Realistic Approach. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP Workshops, 1998, pp:428-437 [Conf]
  19. Francisco José Alfaro, José L. Sánchez, José Duato
    Studying the Influence of the InfiniBand Packet Size to Guarantee QoS. [Citation Graph (0, 0)][DBLP]
    ISCC, 2005, pp:989-994 [Conf]
  20. Raúl Martínez, Francisco José Alfaro, José L. Sánchez
    Studying Several Proposals for the Adaptation of the DTable Scheduler to Advanced Switching. [Citation Graph (0, 0)][DBLP]
    ISPA, 2006, pp:98-112 [Conf]
  21. Lorenzo Moreno, C. S. González, R. M. Aguilar, J. I. Estévez, J. Sánchez, C. Barroso
    Adaptive Multimedia Interface for Users with Intellectual and Cognitive Handicaps. [Citation Graph (0, 0)][DBLP]
    Intelligent Tutoring Systems, 2000, pp:363-372 [Conf]
  22. Lorenzo Moreno, C. S. González, Vanessa Muñoz, J. I. Estévez, R. M. Aguilar, José L. Sánchez, Jose F. Sigut, Jose D. Piñeiro
    Integrating Multimedia Technology, Knowledge Based System and Speech Processing for the Diagnostic and Treatment of Developmental Dyslexia. [Citation Graph (0, 0)][DBLP]
    Intelligent Tutoring Systems, 2002, pp:168-177 [Conf]
  23. Jose D. Piñeiro, Roberto L. Marichal, Lorenzo Moreno, Jose F. Sigut, J. I. Estévez, R. M. Aguilar, José L. Sánchez, Juan J. Merino
    Evoked Potential Feature Detection with Recurrent Dynamic Neural Networks. [Citation Graph (0, 0)][DBLP]
    NC, 1998, pp:533-536 [Conf]
  24. José M. García, José L. Sánchez, Pascual González
    PEPE: A Trace-Driven Simulator to Evaluate Reconfigurable Multicomputer Architectures. [Citation Graph (0, 0)][DBLP]
    PARA, 1996, pp:302-311 [Conf]
  25. José L. Sánchez, José M. García, Joaquin Fernández
    Improving the Performance of Parallel Triangularization of a Sparse Matrix Using a Reconfigurable Multicomputer. [Citation Graph (0, 0)][DBLP]
    PARA, 1995, pp:493-502 [Conf]
  26. Pedro Javier García, Francisco J. Quiles, Francisco José Alfaro, José L. Sánchez, José Duato
    An analysis of deadlock risk during centralized network mapping. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2004, pp:601-606 [Conf]
  27. Raúl Martínez, José L. Sánchez, Francisco José Alfaro, Vicente Chirivella, Jose Flich
    Studying the Effect of the Design Parameters on the Interconnection Network Performance in NOWs. [Citation Graph (0, 0)][DBLP]
    PDP, 2005, pp:102-109 [Conf]
  28. Pascual González, José L. Sánchez, Francisco José Alfaro
    An Efficient Load Balancing Method for Parallel Ray Tracing on Heterogeneous Workstation Networks. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1999, pp:2622-2628 [Conf]
  29. Francisco José Alfaro, José A. Gallud, José L. Sánchez
    A Function to Dynamic Workload Allocation in Distributed Applications. [Citation Graph (0, 0)][DBLP]
    PVM/MPI, 1997, pp:219-225 [Conf]
  30. Lorenzo Moreno, J. I. Estévez, R. M. Aguilar, José L. Sánchez, Jose F. Sigut, Jose D. Piñeiro, Roberto L. Marichal
    Automatic analysis of signals with symbolic content. [Citation Graph (0, 0)][DBLP]
    Artificial Intelligence in Medicine, 2000, v:18, n:3, pp:245- [Journal]
  31. Lorenzo Moreno, Jose D. Piñeiro, José L. Sánchez, Soledad Mañas, Juan J. Merino, Leopoldo Acosta, Alberto F. Hamilton
    Using neural networks to improve classification: Application to brain maturation. [Citation Graph (0, 0)][DBLP]
    Neural Networks, 1995, v:8, n:5, pp:815-820 [Journal]
  32. Lorenzo Moreno, R. M. Aguilar, C. A. Martín, Jose D. Piñeiro, J. I. Estévez, Jose F. Sigut, José L. Sánchez, V. I. Jiménez
    Patient-centered simulation tool for aiding in hospital management. [Citation Graph (0, 0)][DBLP]
    Simul. Pr. Theory, 1999, v:7, n:4, pp:373-393 [Journal]
  33. Francisco José Alfaro, José L. Sánchez, José Duato
    QoS in InfiniBand Subnetworks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:9, pp:810-823 [Journal]
  34. Rafael Casado, Aurelio Bermúdez, José Duato, Francisco J. Quiles, José L. Sánchez
    A Protocol for Deadlock-Free Dynamic Reconfiguration in High-Speed Local Area Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:2, pp:115-132 [Journal]
  35. Alejandro Martínez-Vicente, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, Jose Flich, Francisco J. Quiles, José Duato
    Integrated QoS Provision and Congestion Management for Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2007, pp:837-847 [Conf]
  36. Raúl Martínez, Francisco José Alfaro, José L. Sánchez
    Comparing the latency performance of the DTable and DRR schedulers. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  37. Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato
    Deadline-based QoS Algorithms for High-performance Networks. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-9 [Conf]
  38. Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato
    Efficient Switches with QoS Support for Clusters. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  39. Raúl Martínez, Francisco José Alfaro, José L. Sánchez
    Implementing the Advanced Switching Minimum Bandwidth Egress Link Scheduler. [Citation Graph (0, 0)][DBLP]
    NCA, 2006, pp:118-125 [Conf]
  40. Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, José Duato
    Full QoS Support with 2 VCs for Single-chip Switches. [Citation Graph (0, 0)][DBLP]
    NCA, 2006, pp:239-242 [Conf]
  41. Alejandro Martínez, Raúl Martínez, Francisco José Alfaro, José L. Sánchez
    A low-cost strategy to provide full QoS support in Advanced Switching networks. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:7, pp:355-368 [Journal]
  42. Francisco José Alfaro, José L. Sánchez, M. Menduiña, José Duato
    A Formal Model to Manage the InfiniBand Arbitration Tables Providing QoS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:8, pp:1024-1039 [Journal]
  43. Alejandro Martínez, Francisco José Alfaro, José L. Sánchez, Francisco J. Quiles, José Duato
    A New Cost-Effective Technique for QoS Support in Clusters. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:12, pp:1714-1726 [Journal]

  44. Hardware Implementation Study of the SCFQ-CA and DRR-CA Scheduling Algorithms. [Citation Graph (, )][DBLP]


  45. Providing Full QoS with 2 VCs in High-Speed Switches. [Citation Graph (, )][DBLP]


  46. Hardware Implementation Study of the Deficit Table Egress Link Scheduling Algorithm. [Citation Graph (, )][DBLP]


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