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David Brooks: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David Brooks, Margaret Martonosi
    Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware. [Citation Graph (0, 0)][DBLP]
    CANPC, 1999, pp:181-195 [Conf]
  2. Lukasz Strozek, David Brooks
    Efficient architectures through application clustering and architectural heterogeneity. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:190-200 [Conf]
  3. Mark Hempstead, Gu-Yeon Wei, David Brooks
    Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:368-378 [Conf]
  4. Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook
    A circuit level implementation of an adaptive issue queue for power-aware microprocessors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:73-78 [Conf]
  5. David Brooks, Margaret Martonosi
    Dynamic Thermal Management for High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2001, pp:171-0 [Conf]
  6. David Brooks, Margaret Martonosi
    Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:13-22 [Conf]
  7. Russ Joseph, David Brooks, Margaret Martonosi
    Control Techniques to Eliminate Voltage Emergencies in High Performance Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:79-90 [Conf]
  8. Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron
    Performance, Energy, and Thermal Considerations for SMT and CMP Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:71-82 [Conf]
  9. Xiaoyao Liang, David Brooks
    Microarchitecture parameter selection to optimize system performance under process variation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:429-436 [Conf]
  10. Yau Chin, John Sheu, David Brooks
    Evaluating Techniques for Exploiting Instruction Slack. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:375-378 [Conf]
  11. David Brooks, Mark Lee
    Learning Syntax from Function Words. [Citation Graph (0, 0)][DBLP]
    ICGI, 2004, pp:273-274 [Conf]
  12. David Brooks, Vivek Tiwari, Margaret Martonosi
    Wattch: a framework for architectural-level power analysis and optimizations. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:83-94 [Conf]
  13. Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David Brooks
    An Ultra Low Power System Architecture for Sensor Network Applications. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:208-219 [Conf]
  14. Kim M. Hazelwood, David Brooks
    Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:326-331 [Conf]
  15. Yingmin Li, David Brooks, Zhigang Hu, Kevin Skadron, Pradip Bose
    Understanding the energy efficiency of simultaneous multithreading. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:44-49 [Conf]
  16. Yingmin Li, Mark Hempstead, Patrick Mauro, David Brooks, Zhigang Hu, Kevin Skadron
    Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:173-178 [Conf]
  17. Mark Hempstead, Matt Welsh, David Brooks
    TinyBench: The Case For A Standardized Benchmark Suite for TinyOS Based Wireless Sensor Network Devices. [Citation Graph (0, 0)][DBLP]
    LCN, 2004, pp:585-586 [Conf]
  18. James Ellsmere, Jeffrey A. Stoll, David W. Rattner, David Brooks, Robert Kane, William M. Wells III, Ron Kikinis, Kirby Vosburgh
    A Navigation System for Augmenting Laparoscopic Ultrasound. [Citation Graph (0, 0)][DBLP]
    MICCAI (2), 2003, pp:184-191 [Conf]
  19. Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma
    Optimizing pipelines for power and performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:333-344 [Conf]
  20. Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
    A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:271-282 [Conf]
  21. Xiaoyao Liang, David Brooks
    Mitigating the Impact of Process Variations on Processor Register Files and Execution Units. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:504-514 [Conf]
  22. Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas
    Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:1-17 [Conf]
  23. David Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose
    Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:126-136 [Conf]
  24. Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi
    An Adaptive Issue Queue for Reduced Power at High Performance. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:25-39 [Conf]
  25. Wai-Chi Fang, Sharon Kedar, Susan Owen, Gu-Yeon Wei, David Brooks, Jonathan Lees
    System-on-Chip Architecture Design for Intelligent Sensor Networks. [Citation Graph (0, 0)][DBLP]
    IIH-MSP, 2006, pp:579-582 [Conf]
  26. David Brooks, Pradip Bose, Viji Srinivasan, Michael Gschwind, Philip G. Emma, Michael G. Rosenfield
    New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:5-6, pp:653-670 [Journal]
  27. David Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook
    Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:6, pp:26-44 [Journal]
  28. Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
    Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:119-129 [Journal]
  29. David Brooks, Pradip Bose, Margaret Martonosi
    Power-performance simulation: design and validation strategies. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS Performance Evaluation Review, 2004, v:31, n:4, pp:13-18 [Journal]
  30. Victor V. Zyuban, David Brooks, Viji Srinivasan, Michael Gschwind, Pradip Bose, Philip N. Strenski, Philip G. Emma
    Integrated Analysis of Power and Performance for Pipelined Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:8, pp:1004-1016 [Journal]
  31. David Brooks, Margaret Martonosi
    Value-based clock gating and operation packing: dynamic strategies for improving processor power and performance. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 2000, v:18, n:2, pp:89-126 [Journal]
  32. David Brooks, Robert P. Dick, Russ Joseph, Li Shang
    Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:3, pp:49-62 [Journal]

  33. Efficiency trends and limits from comprehensive microarchitectural adaptivity. [Citation Graph (, )][DBLP]


  34. An accelerator-based wireless sensor network processor in 130nm CMOS. [Citation Graph (, )][DBLP]


  35. System level analysis of fast, per-core DVFS using on-chip switching regulators. [Citation Graph (, )][DBLP]


  36. Voltage emergency prediction: Using signatures to reduce operating margins. [Citation Graph (, )][DBLP]


  37. CMP design space exploration subject to physical constraints. [Citation Graph (, )][DBLP]


  38. Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. [Citation Graph (, )][DBLP]


  39. Evaluation of voltage interpolation to address process variations. [Citation Graph (, )][DBLP]


  40. ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency. [Citation Graph (, )][DBLP]


  41. Thread motion: fine-grained power management for multi-core systems. [Citation Graph (, )][DBLP]


  42. System design considerations for sensor network applications. [Citation Graph (, )][DBLP]


  43. Towards a software approach to mitigate voltage emergencies. [Citation Graph (, )][DBLP]


  44. Instruction-driven clock scheduling with glitch mitigation. [Citation Graph (, )][DBLP]


  45. The design of a bloom filter hardware accelerator for ultra low power systems. [Citation Graph (, )][DBLP]


  46. Place and route considerations for voltage interpolated designs. [Citation Graph (, )][DBLP]


  47. Process Variation Tolerant 3T1D-Based Cache Architectures. [Citation Graph (, )][DBLP]


  48. CPR: Composable performance regression for scalable multiprocessor models. [Citation Graph (, )][DBLP]


  49. Tribeca: design for PVT variations with local recovery and fine-grained adaptation. [Citation Graph (, )][DBLP]


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