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François-Xavier Standaert: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gilles Piret, François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater
    On the Security of the DeKaRT Primitive. [Citation Graph (0, 0)][DBLP]
    CARDIS, 2004, pp:241-254 [Conf]
  2. François-Xavier Standaert, Gilles Piret, Neil Gershenfeld, Jean-Jacques Quisquater
    SEA: A Scalable Encryption Algorithm for Small Embedded Applications. [Citation Graph (0, 0)][DBLP]
    CARDIS, 2006, pp:222-236 [Conf]
  3. Eric Peeters, François-Xavier Standaert, Nicolas Donckers, Jean-Jacques Quisquater
    Improved Higher-Order Side-Channel Attacks with FPGA Experiments. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:309-323 [Conf]
  4. François-Xavier Standaert, Siddika Berna Örs, Bart Preneel
    Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? [Citation Graph (0, 0)][DBLP]
    CHES, 2004, pp:30-44 [Conf]
  5. François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
    A Time-Memory Tradeoff Using Distinguished Points: New Analysis & FPGA Results. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:593-609 [Conf]
  6. François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
    Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs. [Citation Graph (0, 0)][DBLP]
    CHES, 2003, pp:334-350 [Conf]
  7. François-Xavier Standaert, Eric Peeters, Cédric Archambeau, Jean-Jacques Quisquater
    Towards Security Limits in Side-Channel Attacks. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:30-45 [Conf]
  8. Cédric Archambeau, Eric Peeters, François-Xavier Standaert, Jean-Jacques Quisquater
    Template Attacks in Principal Subspaces. [Citation Graph (0, 0)][DBLP]
    CHES, 2006, pp:1-14 [Conf]
  9. Gaël Rouvroy, François-Xavier Standaert, Frédéric Lefèbvre, Jean-Jacques Quisquater, Benoit M. Macq, Jean-Didier Legat
    Reconfigurable hardware solutions for the digital rights management of digital cinema. [Citation Graph (0, 0)][DBLP]
    Digital Rights Management Workshop, 2004, pp:40-53 [Conf]
  10. Tal Malkin, François-Xavier Standaert, Moti Yung
    A Comparative Cost/Security Analysis of Fault Attack Countermeasures. [Citation Graph (0, 0)][DBLP]
    FDTC, 2006, pp:159-172 [Conf]
  11. François Koeune, François-Xavier Standaert
    A Tutorial on Physical Security and Side-Channel Attacks. [Citation Graph (0, 0)][DBLP]
    FOSAD, 2004, pp:78-108 [Conf]
  12. Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
    Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:247- [Conf]
  13. François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
    A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:216-224 [Conf]
  14. François Koeune, Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Pierre David, Jean-Didier Legat
    An FPGA Implementation of the Linear Cryptanalysis. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:845-852 [Conf]
  15. Jean-Jacques Quisquater, François-Xavier Standaert, Gaël Rouvroy, Jean-Pierre David, Jean-Didier Legat
    A Cryptanalytic Time-Memory Tradeoff: First FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:780-789 [Conf]
  16. Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
    Design Strategies and Modified Descriptions to Optimize Cipher FPGA Implementations: Fast and Compact Results for DES and Triple-DES. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:181-193 [Conf]
  17. François-Xavier Standaert, Siddika Berna Örs, Jean-Jacques Quisquater, Bart Preneel
    Power Analysis Attacks Against FPGA Implementations of the DES. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:84-94 [Conf]
  18. François-Xavier Standaert, Loïc van Oldeneel tot Oldenzeel, David Samyde, Jean-Jacques Quisquater
    Power Analysis of FPGAs: How Practical is the Attack? [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:701-711 [Conf]
  19. François-Xavier Standaert, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
    ICEBERG : An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FSE, 2004, pp:279-299 [Conf]
  20. Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
    Efficient FPGA Implementation of Block Cipher MISTY1. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:185- [Conf]
  21. Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
    Compact and Efficient Encryption/Decryption Module for FPGA Implementation of the AES Rijndael Very Well Suited for Small Embedded Applications. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2004, pp:583-587 [Conf]
  22. François-Xavier Standaert, Frédéric Lefèbvre, Gaël Rouvroy, Benoit M. Macq, Jean-Jacques Quisquater, Jean-Didier Legat
    Practical Evaluation of a Radial Soft Hash Algorithm. [Citation Graph (0, 0)][DBLP]
    ITCC (2), 2005, pp:89-94 [Conf]
  23. François-Xavier Standaert, Eric Peeters, Jean-Jacques Quisquater
    On the Masking Countermeasure and Higher-Order Power Analysis Attacks. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:562-567 [Conf]
  24. François-Xavier Standaert, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater
    FPGA Implementations of the ICEBERG Block Cipher. [Citation Graph (0, 0)][DBLP]
    ITCC (1), 2005, pp:556-561 [Conf]
  25. François Macé, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
    A Design Methodology for Secured ICs Using Dynamic Current Mode Logic. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:550-560 [Conf]
  26. Eric Peeters, François-Xavier Standaert, Jean-Jacques Quisquater
    Power and electromagnetic analysis: Improved model, consequences and comparisons. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:1, pp:52-60 [Journal]
  27. François-Xavier Standaert, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater
    FPGA implementations of the ICEBERG block cipher. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:1, pp:20-27 [Journal]
  28. Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
    Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:4, pp:473-482 [Journal]
  29. François Macé, François-Xavier Standaert, Jean-Jacques Quisquater
    Information Theoretic Evaluation of Side-Channel Resistant Logic Styles. [Citation Graph (0, 0)][DBLP]
    CHES, 2007, pp:427-442 [Conf]
  30. François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater
    FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  31. Baudoin Collard, François-Xavier Standaert, Jean-Jacques Quisquater
    Improving the Time Complexity of Matsui's Linear Cryptanalysis. [Citation Graph (0, 0)][DBLP]
    ICISC, 2007, pp:77-88 [Conf]
  32. François-Xavier Standaert, François Macé, Eric Peeters, Jean-Jacques Quisquater
    Updates on the Security of FPGAs Against Power Analysis Attacks. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:335-346 [Conf]

  33. Multi-trail Statistical Saturation Attacks. [Citation Graph (, )][DBLP]


  34. How to Compare Profiled Side-Channel Attacks?. [Citation Graph (, )][DBLP]


  35. Adaptive Chosen-Message Side-Channel Attacks. [Citation Graph (, )][DBLP]


  36. A block cipher based pseudo random number generator secure against side-channel key recovery. [Citation Graph (, )][DBLP]


  37. Using Subspace-Based Template Attacks to Compare and Combine Power and Electromagnetic Information Leakages. [Citation Graph (, )][DBLP]


  38. Mutual Information Analysis: How, When and Why?. [Citation Graph (, )][DBLP]


  39. Algebraic Side-Channel Attacks on the AES: Why Time also Matters in DPA. [Citation Graph (, )][DBLP]


  40. A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. [Citation Graph (, )][DBLP]


  41. Improved and Multiple Linear Cryptanalysis of Reduced Round Serpent. [Citation Graph (, )][DBLP]


  42. A Statistical Saturation Attack against the Block Cipher PRESENT. [Citation Graph (, )][DBLP]


  43. A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks. [Citation Graph (, )][DBLP]


  44. Experiments on the Multiple Linear Cryptanalysis of Reduced Round Serpent. [Citation Graph (, )][DBLP]


  45. Partition vs. Comparison Side-Channel Distinguishers: An Empirical Evaluation of Statistical Tests for Univariate Side-Channel Attacks against Two Unprotected CMOS Devices. [Citation Graph (, )][DBLP]


  46. The Swiss-Knife RFID Distance Bounding Protocol. [Citation Graph (, )][DBLP]


  47. Implementation of the AES-128 on Virtex-5 FPGAs. [Citation Graph (, )][DBLP]


  48. Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices. [Citation Graph (, )][DBLP]


  49. Does Physical Security of Cryptographic Devices Need a Formal Study? (Invited Talk). [Citation Graph (, )][DBLP]


  50. On the Energy Cost of Communication and Cryptography in Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  51. How Leaky Is an Extractor? [Citation Graph (, )][DBLP]


  52. Provable security of block ciphers against linear cryptanalysis: a mission impossible? [Citation Graph (, )][DBLP]


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