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Sylvain Guilley: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet
    Differential Power Analysis Model and Some Results. [Citation Graph (0, 0)][DBLP]
    CARDIS, 2004, pp:127-142 [Conf]
  2. Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet
    The "Backend Duplication" Method. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:383-397 [Conf]
  3. Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost
    CMOS Structures Suitable for Secured Hardware. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1414-1415 [Conf]
  4. Sylvain Guilley, Philippe Hoogvorst
    The Proof by 2M-1: a Low-Cost Method to Check Arithmetic Computations. [Citation Graph (0, 0)][DBLP]
    SEC, 2005, pp:589-600 [Conf]
  5. Philippe Hoogvorst, Sylvain Guilley, Sumanta Chau, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet
    A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:15-22 [Conf]
  6. Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet
    A fast pipelined multi-mode DES architecture operating in IP representation. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:479-489 [Journal]

  7. Deconvolving Protected Signals. [Citation Graph (, )][DBLP]


  8. Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks. [Citation Graph (, )][DBLP]


  9. An 8x8 run-time reconfigurable FPGA embedded in a SoC. [Citation Graph (, )][DBLP]


  10. Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. [Citation Graph (, )][DBLP]


  11. Far Correlation-based EMA with a precharacterized leakage model. [Citation Graph (, )][DBLP]


  12. BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. [Citation Graph (, )][DBLP]


  13. Practical Setup Time Violation Attacks on AES. [Citation Graph (, )][DBLP]


  14. Silicon-level Solutions to Counteract Passive and Active Attacks. [Citation Graph (, )][DBLP]


  15. WDDL is Protected against Setup Time Violation Attacks. [Citation Graph (, )][DBLP]


  16. Efficient tiling patterns for reconfigurable gate arrays. [Citation Graph (, )][DBLP]


  17. Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. [Citation Graph (, )][DBLP]


  18. Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. [Citation Graph (, )][DBLP]


  19. Towards Quantum Key Distribution System using Homodyne Detection with Differential Time-Multiplexed Reference. [Citation Graph (, )][DBLP]


  20. Efficient tiling patterns for reconfigurable gate arrays. [Citation Graph (, )][DBLP]


  21. Physical Design of FPGA Interconnect to Prevent Information Leakage. [Citation Graph (, )][DBLP]


  22. Practical Improvements of Profiled Side-Channel Attacks on a Hardware Crypto-Accelerator. [Citation Graph (, )][DBLP]


  23. Place-and-Route Impact on the Security of DPL Designs in FPGAs. [Citation Graph (, )][DBLP]


  24. Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs. [Citation Graph (, )][DBLP]


  25. Fault Analysis Attack on an FPGA AES Implementation. [Citation Graph (, )][DBLP]


  26. DPL on Stratix II FPGA: What to Expect?. [Citation Graph (, )][DBLP]


  27. Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. [Citation Graph (, )][DBLP]


  28. Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. [Citation Graph (, )][DBLP]


  29. Defeating Any Secret Cryptography with SCARE Attacks. [Citation Graph (, )][DBLP]


  30. A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks [Citation Graph (, )][DBLP]


  31. Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. [Citation Graph (, )][DBLP]


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