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Philippe Hoogvorst:
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Publications of Author
- Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet
Differential Power Analysis Model and Some Results. [Citation Graph (0, 0)][DBLP] CARDIS, 2004, pp:127-142 [Conf]
- Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet
The "Backend Duplication" Method. [Citation Graph (0, 0)][DBLP] CHES, 2005, pp:383-397 [Conf]
- Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost
CMOS Structures Suitable for Secured Hardware. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1414-1415 [Conf]
- Philippe Hoogvorst, Ronan Keryell, Philippe Matherat, Nicolas Paris
POMP or How to Design a Massively Parallel Machine with Small Developments. [Citation Graph (0, 0)][DBLP] PARLE (1), 1991, pp:83-100 [Conf]
- Sylvain Guilley, Philippe Hoogvorst
The Proof by 2M-1: a Low-Cost Method to Check Arithmetic Computations. [Citation Graph (0, 0)][DBLP] SEC, 2005, pp:589-600 [Conf]
- Philippe Hoogvorst, Sylvain Guilley, Sumanta Chau, Alin Razafindraibe, Taha Beyrouthy, Laurent Fesquet
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. [Citation Graph (0, 0)][DBLP] ReCoSoC, 2007, pp:15-22 [Conf]
- Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet
A fast pipelined multi-mode DES architecture operating in IP representation. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:4, pp:479-489 [Journal]
An 8x8 run-time reconfigurable FPGA embedded in a SoC. [Citation Graph (, )][DBLP]
Efficient tiling patterns for reconfigurable gate arrays. [Citation Graph (, )][DBLP]
Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic. [Citation Graph (, )][DBLP]
Efficient tiling patterns for reconfigurable gate arrays. [Citation Graph (, )][DBLP]
Physical Design of FPGA Interconnect to Prevent Information Leakage. [Citation Graph (, )][DBLP]
Place-and-Route Impact on the Security of DPL Designs in FPGAs. [Citation Graph (, )][DBLP]
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks [Citation Graph (, )][DBLP]
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. [Citation Graph (, )][DBLP]
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