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Publications of Author

1. Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin
   Compiler Directed Early Register Release. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2005, pp:110-122 [Conf]
   
2. Enric Gibert, Jaume Abella, F. Jesús Sánchez, Xavier Vera, Antonio González
   Variable-Based Multi-module Data Caches for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2005, pp:207-217 [Conf]
   
3. Xavier Vera, Jaume Abella, Antonio González, Josep Llosa
   Optimizing Program Locality Through CMEs and GAs. [Citation Graph (0, 0)][DBLP]
   IEEE PACT, 2003, pp:68-78 [Conf]
   
4. Jaume Abella, Antonio González
   Power-Aware Adaptive Issue Queue and Register File. [Citation Graph (0, 0)][DBLP]
   HiPC, 2003, pp:34-43 [Conf]
   
5. Jaume Abella, Antonio González
   Low-Complexity Distributed Issue Queue. [Citation Graph (0, 0)][DBLP]
   HPCA, 2004, pp:73-83 [Conf]
   
6. Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González
   Software Directed Issue Queue Power Reduction. [Citation Graph (0, 0)][DBLP]
   HPCA, 2005, pp:144-153 [Conf]
   
7. Jaume Abella, Antonio González
   Power Efficient Data Cache Designs. [Citation Graph (0, 0)][DBLP]
   ICCD, 2003, pp:8-13 [Conf]
   
8. Jaume Abella, Antonio González
   On Reducing Register Pressure and Energy in Multiple-Banked Register Files. [Citation Graph (0, 0)][DBLP]
   ICCD, 2003, pp:14-20 [Conf]
   
9. Alex Vallejo, Agustin Zaballos, Jaume Abella, Joseph M. Selga, Carles Duz
   Performance of a Policy-Based Management System in IPv6 Networks Using COPS-PR. [Citation Graph (0, 0)][DBLP]
   ICN, 2007, pp:37- [Conf]
   
10. Jaume Abella, Antonio González, Josep Llosa, Xavier Vera
    Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2002, pp:568-580 [Conf]
    
11. Jaume Abella, Antonio González
    Heterogeneous way-size cache. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:239-248 [Conf]
    
12. Guiomar Corral, Albert Fornells, Elisabet Golobardes, Jaume Abella
    Cohesion Factors: Improving the Clustering Capabilities of Consensus. [Citation Graph (0, 0)][DBLP]
    IDEAL, 2006, pp:488-495 [Conf]
    
13. Jaume Abella, Antonio González
    Inherently Workload-Balanced Clustered Microarchitecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
    
14. Jaume Abella, Antonio González
    SAMIE-LSQ: set-associative multiple-instruction entry load/store queue. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
    
15. Joan Ruiz, Alex Vallejo, Jaume Abella
    IPv6 Conformance and Interoperability Testing. [Citation Graph (0, 0)][DBLP]
    ISCC, 2005, pp:83-88 [Conf]
    
16. Jaume Abella, Ramon Canal, Antonio González
    Power- and Complexity-Aware Issue Queue Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:50-58 [Journal]
    
17. Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle
    IATAC: a smart predictor to turn-off L2 cache lines. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:1, pp:55-77 [Journal]
    
18. Xavier Vera, Jaume Abella, Josep Llosa, Antonio González
    An accurate cost model for guiding data locality transformations. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2005, v:27, n:5, pp:946-987 [Journal]
    
19. Xavier Vera, Jaume Abella
    Surviving to Errors in Multi-Core Environments. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:260- [Conf]
    
20. Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González
    Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:15-22 [Conf]
    
21. 
    The split register file. [Citation Graph (, )][DBLP]
    
    
22. 
    Issue system protection mechanisms. [Citation Graph (, )][DBLP]
    
    
23. 
    On-Line Failure Detection and Confinement in Caches. [Citation Graph (, )][DBLP]
    
    
24. 
    Online error detection and correction of erratic bits in register files. [Citation Graph (, )][DBLP]
    
    
25. 
    End-to-end register data-flow continuous self-test. [Citation Graph (, )][DBLP]
    
    
26. 
    Model for polling in noisy multihop systems with application to PLC and AMR. [Citation Graph (, )][DBLP]
    
    
27. 
    Penelope: The NBTI-Aware Processor. [Citation Graph (, )][DBLP]
    
    
28. 
    Low Vccmin fault-tolerant cache with highly predictable performance. [Citation Graph (, )][DBLP]
    
    
29. 
    Electromigration for microarchitects. [Citation Graph (, )][DBLP]