The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Antonio González: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin
    Compiler Directed Early Register Release. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:110-122 [Conf]
  2. Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli
    Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:281-290 [Conf]
  3. Enric Gibert, Jaume Abella, F. Jesús Sánchez, Xavier Vera, Antonio González
    Variable-Based Multi-module Data Caches for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2005, pp:207-217 [Conf]
  4. José González, Antonio González
    Control-Flow Speculation through Value Prediction for Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:57-65 [Conf]
  5. Ramon Canal, Joan-Manuel Parcerisa, Antonio González
    A Cost-Effective Clustered Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:160-168 [Conf]
  6. Josep M. Codina, F. Jesús Sánchez, Antonio González
    A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:175-184 [Conf]
  7. Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González, José Duato
    Efficient Interconnects for Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2002, pp:291-0 [Conf]
  8. F. Jesús Sánchez, Antonio González
    Fast, Accurate and Flexible Data Locality Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:124-129 [Conf]
  9. F. Jesús Sánchez, Antonio González, Mateo Valero
    Static Locality Analysis for Cache Management. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1997, pp:261-271 [Conf]
  10. Xavier Vera, Jaume Abella, Antonio González, Josep Llosa
    Optimizing Program Locality Through CMEs and GAs. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2003, pp:68-78 [Conf]
  11. Chris M. Roadknight, Antonio González, Laura Parrot, Steve Boult, Ian W. Marshall
    An Intelligent Sensor Network for Oceanographic Data Acquisition. [Citation Graph (0, 0)][DBLP]
    ADHOC-NOW, 2005, pp:235-243 [Conf]
  12. Jordi Tubella, Antonio González
    Combining depth-first and breadth-first search in Prolog execution. [Citation Graph (0, 0)][DBLP]
    GULP-PRODE (2), 1994, pp:452-453 [Conf]
  13. Dolors Royo, Miguel Valero-García, Antonio González, Carme Mari
    A Methodology for User-Oriented Scalability Analysis. [Citation Graph (0, 0)][DBLP]
    ASAP, 1997, pp:304-315 [Conf]
  14. Ramon Canal, Antonio González, James E. Smith
    Software-Controlled Operand-Gating. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:125-136 [Conf]
  15. Enric Gibert, F. Jesús Sánchez, Antonio González
    Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache. [Citation Graph (0, 0)][DBLP]
    CGO, 2003, pp:193-203 [Conf]
  16. Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
    Heterogeneous Clustered VLIW Microarchitectures. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:354-366 [Conf]
  17. Josep M. Codina, F. Jesús Sánchez, Antonio González
    Virtual Cluster Scheduling Through the Scheduling Graph. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:89-101 [Conf]
  18. Silvia Acid, Luis M. de Campos, Antonio González, Rafael Molina, Nicolas Pérez de la Blanca
    Learning with CASTLE. [Citation Graph (0, 0)][DBLP]
    ECSQARU, 1991, pp:99-106 [Conf]
  19. Pedro Marcuello, Antonio González
    Data Speculative Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10321-10324 [Conf]
  20. Joan-Manuel Parcerisa, Antonio González
    The Latency Hiding Effectiveness of Decoupled Access/Execute Processors. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1998, pp:10293-10300 [Conf]
  21. Carles Aliagas, Carlos Molina, Montse Garcia, Antonio González, Jordi Tubella
    Value Compression to Reduce Power in Data Caches. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2003, pp:616-622 [Conf]
  22. Ramon Canal, Antonio González, James E. Smith
    Value Compression for Efficient Computation. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2005, pp:519-529 [Conf]
  23. Luis Díaz de Cerio, Miguel Valero-García, Antonio González
    Complete Exchange Algorithms for Meshes and Tori Using a Systematic Approach (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:591-594 [Conf]
  24. Luis Díaz de Cerio, Miguel Valero-García, Antonio González
    Overlapping Communication and Computation in Hypercubes. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:253-257 [Conf]
  25. José González, Antonio González
    Memory Address Prediction for Data Speculation. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:1084-1091 [Conf]
  26. Antonio Martínez, Fracisco Fraile, Jordi Mallorquí, Leonardo Nogueira, Jordi Gabaldá, Antoni Broquetas, Antonio González
    PARSAR: Parallelisation of a Chirp Scaling Algorithm SAR Processor. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1997, pp:1346-1350 [Conf]
  27. Miguel Valero-García, Antonio González, Luis Díaz de Cerio, Dolors Royo
    Divide-and-Conquer Algorithms on Two-Dimensional Meshes. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:1051-1056 [Conf]
  28. Xavier Vera, Josep Llosa, Antonio González, Nerina Bermudo
    A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:194-198 [Conf]
  29. Jaume Abella, Antonio González
    Power-Aware Adaptive Issue Queue and Register File. [Citation Graph (0, 0)][DBLP]
    HiPC, 2003, pp:34-43 [Conf]
  30. Juan L. Aragón, José González, José M. García, Antonio González
    Confidence Estimation for Branch Prediction Reversal. [Citation Graph (0, 0)][DBLP]
    HiPC, 2001, pp:214-223 [Conf]
  31. Jaume Abella, Antonio González
    Low-Complexity Distributed Issue Queue. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:73-83 [Conf]
  32. Juan L. Aragón, José González, Antonio González
    Power-Aware Control Speculation through Selective Throttling. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:103-112 [Conf]
  33. Antonio González, José González, Mateo Valero
    Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:175-184 [Conf]
  34. Ramon Canal, Joan-Manuel Parcerisa, Antonio González
    Dynamic Cluster Assignment Mechanisms. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:133-0 [Conf]
  35. Pedro Chaparro, Grigorios Magklis, José González, Antonio González
    Distributing the Frontend for Temperature Reduction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:61-70 [Conf]
  36. Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González
    Software Directed Issue Queue Power Reduction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:144-153 [Conf]
  37. Joan-Manuel Parcerisa, Antonio González
    The Synergy of Multithreading and Access/Execute Decoupling. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:59-63 [Conf]
  38. Pedro Marcuello, Antonio González
    Thread-Spawning Schemes for Speculative Multithreading. [Citation Graph (0, 0)][DBLP]
    HPCA, 2002, pp:55-64 [Conf]
  39. Jordi Tubella, Antonio González
    Control Speculation in Multithreaded Processors through Dynamic Loop Detection. [Citation Graph (0, 0)][DBLP]
    HPCA, 1998, pp:14-23 [Conf]
  40. Pedro Marcuello, Antonio González
    Exploiting Speculative Thread-Level Parallelism on a SMT Processor. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1999, pp:754-763 [Conf]
  41. Carlos Molina, Antonio González, Jordi Tubella
    Reducing Memory Traffic Via Redundant Store Instructions. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1999, pp:1246-1249 [Conf]
  42. Luis A. Castillo, Antonio González
    A Nonlinear Planner for Solving Sequential Control Problems in Manufacturing Systems. [Citation Graph (0, 0)][DBLP]
    IBERAMIA, 1998, pp:409-420 [Conf]
  43. Jaume Abella, Antonio González
    Power Efficient Data Cache Designs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:8-13 [Conf]
  44. Jaume Abella, Antonio González
    On Reducing Register Pressure and Energy in Multiple-Banked Register Files. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:14-20 [Conf]
  45. Juan L. Aragón, José González, José M. García, Antonio González
    Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:228-233 [Conf]
  46. Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González
    Memory Bank Predictors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:666-670 [Conf]
  47. Pedro Chaparro, José González, Antonio González
    Thermal-Aware Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:48-53 [Conf]
  48. José González, Antonio González
    Dynamic Cluster Resizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:375-0 [Conf]
  49. Grigorios Magklis, José González, Antonio González
    Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:250-255 [Conf]
  50. Carlos Molina, Antonio González, Jordi Tubella
    Trace-Level Speculative Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:402-407 [Conf]
  51. Antonio González, Jordi Tubella, Carlos Molina
    Trace-Level Reuse. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:30-0 [Conf]
  52. Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
    Hardware Schemes for Early Register Release. [Citation Graph (0, 0)][DBLP]
    ICPP, 2002, pp:5-13 [Conf]
  53. F. Jesús Sánchez, Antonio González
    The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:555-0 [Conf]
  54. Jaume Abella, Antonio González, Josep Llosa, Xavier Vera
    Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2002, pp:568-580 [Conf]
  55. Juan L. Aragón, José González, Antonio González, James E. Smith
    Dual path instruction processing. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:220-229 [Conf]
  56. Ramon Canal, Antonio González
    A low-complexity issue logic. [Citation Graph (0, 0)][DBLP]
    ICS, 2000, pp:327-335 [Conf]
  57. Ramon Canal, Antonio González
    Reducing the complexity of the issue logic. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:312-320 [Conf]
  58. Josep M. Codina, Josep Llosa, Antonio González
    A comparative study of modulo scheduling techniques. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:97-106 [Conf]
  59. Enric Gibert, F. Jesús Sánchez, Antonio González
    An interleaved cache clustered VLIW processor. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:210-219 [Conf]
  60. Antonio González, Carlos Aliagas, Mateo Valero
    A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1995, pp:338-347 [Conf]
  61. José González, Antonio González
    Speculative Execution via Address Prediction and Data Prefetching. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:196-203 [Conf]
  62. José González, Antonio González
    The Potential of Data Value Speculation to Boost ILP. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:21-28 [Conf]
  63. Antonio González, José M. Llabería
    Instruction fetch unit for parallel execution of branch instructions. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:417-426 [Conf]
  64. Antonio González, Mateo Valero, Nigel P. Topham, Joan-Manuel Parcerisa
    Eliminating Cache Conflict Misses through XOR-Based Placement Functions. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:76-83 [Conf]
  65. Fernando Latorre, José González, Antonio González
    Back-end assignment schemes for clustered multithreaded processors. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:316-325 [Conf]
  66. Carlos Molina, Antonio González, Jordi Tubella
    Dynamic removal of redundant computations. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:474-481 [Conf]
  67. Pedro Marcuello, Antonio González
    Clustered speculative multithreaded processors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:365-372 [Conf]
  68. Pedro Marcuello, Antonio González, Jordi Tubella
    Speculative Multithreaded Processors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:77-84 [Conf]
  69. Jaume Abella, Antonio González
    Heterogeneous way-size cache. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:239-248 [Conf]
  70. F. Jesús Sánchez, Antonio González
    A locality sensitive multi-module cache with explicit management. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:51-59 [Conf]
  71. Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González
    Selective predicate prediction for out-of-order processors. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:46-54 [Conf]
  72. Matteo Monchiero, Ramon Canal, Antonio González
    Design space exploration for multicore architectures: a power/performance/thermal view. [Citation Graph (0, 0)][DBLP]
    ICS, 2006, pp:177-186 [Conf]
  73. Jordi Tubella, Antonio González
    A Partial Breadth-First Execution Model for Prolog. [Citation Graph (0, 0)][DBLP]
    ICTAI, 1994, pp:129-137 [Conf]
  74. Mario Marrero, Celso Perdomo, Jorge Rodríguez, Antonio González
    Collaborative Work Tools in Learning Environments. [Citation Graph (0, 0)][DBLP]
    Information Technology in Educational Management, 2002, pp:129-138 [Conf]
  75. Antonio González, María Amparo Vila Miranda
    An Interval-Based Approach for Working With Fuzzy Numbers. [Citation Graph (0, 0)][DBLP]
    IPMU, 1990, pp:193-202 [Conf]
  76. Jaume Abella, Antonio González
    Inherently Workload-Balanced Clustered Microarchitecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  77. Pedro Marcuello, Antonio González
    A Quantitative Assessment of Thread-Level Speculation Techniques. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:595-0 [Conf]
  78. Alex Pajuelo, Antonio González, Mateo Valero
    Control-Flow Independence Reuse via Dynamic Vectorization. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  79. Dolors Royo, Antonio González, Miguel Valero-García
    Jacobi Orderings for Multi-Port Hypercubes. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:88-97 [Conf]
  80. Jaume Abella, Antonio González
    SAMIE-LSQ: set-associative multiple-instruction entry load/store queue. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  81. Osman S. Unsal, Oguz Ergin, Xavier Vera, Antonio González
    Empowering a helper cluster through data-width aware instruction selection policies. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  82. José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham
    Multiple-banked register file architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:316-325 [Conf]
  83. Daniele Folegnani, Antonio González
    Energy-effective issue logic. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:230-239 [Conf]
  84. Alex Pajuelo, Antonio González, Mateo Valero
    Speculative Dynamic Vectorization. [Citation Graph (0, 0)][DBLP]
    ISCA, 2002, pp:271-280 [Conf]
  85. Carlos Molina, Carles Aliagas, Montse Garcia, Antonio González, Jordi Tubella
    Non redundant data cache. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:274-277 [Conf]
  86. Grigorios Magklis, Pedro Chaparro, José González, Antonio González
    Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:49-54 [Conf]
  87. F. Jesús Sánchez, Antonio González
    Instruction Scheduling for Clustered VLIW Architectures. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:41-46 [Conf]
  88. Luis A. Castillo, Juan Fernández-Olivares, Antonio González
    Some Issues about the Representation and Exploitation of Imprecise Temporal Knowledge for an AI Planner. [Citation Graph (0, 0)][DBLP]
    KES, 2003, pp:1321-1328 [Conf]
  89. Xavier Vera, Josep Llosa, Antonio González
    Near-Optimal Padding for Removing Conflict Misses. [Citation Graph (0, 0)][DBLP]
    LCPC, 2002, pp:329-343 [Conf]
  90. Rafael Muñoz-Salinas, Eugenio Aguirre, Miguel García-Silvente, Antonio González
    People Detection and Tracking Through Stereo Vision for Human-Robot Interaction. [Citation Graph (0, 0)][DBLP]
    MICAI, 2005, pp:337-346 [Conf]
  91. Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
    Instruction Replication for Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:326-338 [Conf]
  92. Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González
    Graph-partitioning based instruction scheduling for clustered processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:150-159 [Conf]
  93. Ramon Canal, Antonio González, James E. Smith
    Very low power pipelines using significance compression. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:181-190 [Conf]
  94. Enric Gibert, F. Jesús Sánchez, Antonio González
    Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:123-133 [Conf]
  95. Enric Gibert, F. Jesús Sánchez, Antonio González
    Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:315-325 [Conf]
  96. Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
    Hypernode reduction modulo scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:350-360 [Conf]
  97. Joan-Manuel Parcerisa, Antonio González
    Reducing wire delay penalty through value prediction. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:317-326 [Conf]
  98. Pedro Marcuello, Jordi Tubella, Antonio González
    Value Prediction for Speculative Multithreaded Architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:230-0 [Conf]
  99. Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
    Delaying Physical Register Allocation through Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:186-0 [Conf]
  100. F. Jesús Sánchez, Antonio González
    Modulo scheduling for a fully-distributed clustered VLIW architecture. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:124-133 [Conf]
  101. F. Jesús Sánchez, Antonio González
    Cache Sensitive Modulo Scheduling. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:338-348 [Conf]
  102. Nigel P. Topham, Antonio González, José González
    The Design and Performance of a Conflict-Avoiding Cache. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:71-80 [Conf]
  103. Enric Fontdecaba, Antonio González, Jesús Labarta
    Load Balancing in a Network Flow Optimization Code. [Citation Graph (0, 0)][DBLP]
    PARA, 1995, pp:214-222 [Conf]
  104. Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González
    The Mitosis Speculative Multithreaded Architectures. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:27-40 [Conf]
  105. Jordi Tubella, Antonio González
    Exploiting path parallelism in logic programming. [Citation Graph (0, 0)][DBLP]
    PDP, 1995, pp:164-173 [Conf]
  106. Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
    Demystifying on-the-fly spill code. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:180-189 [Conf]
  107. Carlos García Quiñones, Carlos Madriles, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen
    Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:269-279 [Conf]
  108. Luis A. Castillo, Juan Fernández-Olivares, Antonio González
    A hybrid hierarchical operator-based planning approach for the design of control programs. [Citation Graph (0, 0)][DBLP]
    PuK, 2000, pp:- [Conf]
  109. Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen
    A framework for modeling and optimization of prescient instruction prefetch. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2003, pp:13-24 [Conf]
  110. José González, Antonio González
    Limits of Instruction Level Parallelism with Data Value Speculation. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1998, pp:452-465 [Conf]
  111. Rafael Muñoz-Salinas, Eugenio Aguirre, Miguel García-Silvente, Antonio González
    Un Sistema Visual Difuso para la Detección de Interés en la Interacción Robot-Persona. [Citation Graph (0, 0)][DBLP]
    Workshop de Agentes Físicos, 2006, pp:49-56 [Conf]
  112. José González, Fernando Latorre, Antonio González
    Cache organizations for clustered microarchitectures. [Citation Graph (0, 0)][DBLP]
    WMPI, 2004, pp:46-55 [Conf]
  113. Luis A. Castillo, Juan Fernández-Olivares, Antonio González
    Automatic generation of control sequences for manufacturing systems based on partial order planning techniques. [Citation Graph (0, 0)][DBLP]
    AI in Engineering, 2000, v:14, n:1, pp:15-30 [Journal]
  114. Luis A. Castillo, Juan Fernández-Olivares, Antonio González
    Un algoritmo de planificación no lineal para la generación automáticade programas industriales. [Citation Graph (0, 0)][DBLP]
    Inteligencia Artificial, Revista Iberoamericana de Inteligencia Artificial, 1999, v:7, n:, pp:40-53 [Journal]
  115. Marc de la Asunción, Luis A. Castillo, Juan Fernández-Olivares, Óscar García-Pérez, Antonio González, Francisco Palao
    SIADEX: An interactive knowledge-based planner for decision support in forest fire fighting. [Citation Graph (0, 0)][DBLP]
    AI Commun., 2005, v:18, n:4, pp:257-268 [Journal]
  116. Eugenio Aguirre, Antonio González
    A Fuzzy Perceptual Model for Ultrasound Sensors Applied to Intelligent Navigation of Mobile Robots. [Citation Graph (0, 0)][DBLP]
    Appl. Intell., 2003, v:19, n:3, pp:171-187 [Journal]
  117. Jordi Tubella, Antonio González, E. Elias
    The Multipath Architecture for Prolog Programs. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1996, v:39, n:9, pp:780-792 [Journal]
  118. Enric Gibert, F. Jesús Sánchez, Antonio González
    Instruction scheduling for a clustered VLIW processor with a word-interleaved cache. [Citation Graph (0, 0)][DBLP]
    Concurrency and Computation: Practice and Experience, 2006, v:18, n:11, pp:1391-1411 [Journal]
  119. Luis Díaz de Cerio, Miguel Valero-García, Antonio González, Dolors Royo
    CALMANT: Un Método Sistemático para la Ejecución de Algoritmos Hipercubo en Sistemas Multiprocesador. [Citation Graph (0, 0)][DBLP]
    Computación y Sistemas, 2001, v:4, n:4, pp:289-297 [Journal]
  120. Luis Díaz de Cerio, Miguel Valero-García, Antonio González, Dolors Royo
    CALMANT: A Systematic Method for the Execution of Hypercube Algorithms in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    Computación y Sistemas, 2001, v:4, n:4, pp:298-305 [Journal]
  121. Luis A. Castillo, Antonio González, Raúl Pérez
    Including a simplicity criterion in the selection of the best rule in a genetic fuzzy learning algorithm. [Citation Graph (0, 0)][DBLP]
    Fuzzy Sets and Systems, 2001, v:120, n:2, pp:309-321 [Journal]
  122. Luis M. de Campos, Antonio González
    A fuzzy inference model based on an uncertainty forward propagation approach. [Citation Graph (0, 0)][DBLP]
    Int. J. Approx. Reasoning, 1993, v:9, n:2, pp:139-164 [Journal]
  123. Lourdes Campos, Antonio González
    Further contributions to the study of the average value for ranking fuzzy numbers. [Citation Graph (0, 0)][DBLP]
    Int. J. Approx. Reasoning, 1994, v:10, n:2, pp:135-153 [Journal]
  124. Eugenio Aguirre, Antonio González
    Fuzzy behaviors for mobile robot navigation: design, coordination and fusion. [Citation Graph (0, 0)][DBLP]
    Int. J. Approx. Reasoning, 2000, v:25, n:3, pp:255-289 [Journal]
  125. Antonio González, Raúl Pérez
    A fuzzy theory refinement algorithm. [Citation Graph (0, 0)][DBLP]
    Int. J. Approx. Reasoning, 1998, v:19, n:3-4, pp:193-220 [Journal]
  126. Antonio González, Olga Pons, María Amparo Vila Miranda
    Dealing with uncertainty and imprecision by means of fuzzy numbers. [Citation Graph (0, 0)][DBLP]
    Int. J. Approx. Reasoning, 1999, v:21, n:3, pp:233-256 [Journal]
  127. Eugenio Aguirre, Antonio González
    Integrating fuzzy topological maps and fuzzy geometric maps for behavior-based robots. [Citation Graph (0, 0)][DBLP]
    Int. J. Intell. Syst., 2002, v:17, n:3, pp:333-368 [Journal]
  128. Olga Pons, Juan C. Cubero, Antonio González, María Amparo Vila Miranda
    Uncertain fuzzy values still in the framework of first-order logi. [Citation Graph (0, 0)][DBLP]
    Int. J. Intell. Syst., 2002, v:17, n:9, pp:873-886 [Journal]
  129. Ramon Canal, Joan-Manuel Parcerisa, Antonio González
    Dynamic Code Partitioning for Clustered Architectures. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2001, v:29, n:1, pp:59-79 [Journal]
  130. Antonio González, María Amparo Vila Miranda
    A discrete method for studying indifference and order relations between fuzzy numbers. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1991, v:56, n:1-3, pp:245-258 [Journal]
  131. Antonio González, Raúl Pérez
    An experimental study about the search mechanism in the SLAVE learning algorithm: Hill-climbing methods versus genetic algorithms. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 2001, v:136, n:1-4, pp:159-174 [Journal]
  132. Antonio González, María Amparo Vila Miranda
    Dominance relations on fuzzy numbers. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 1992, v:64, n:1-2, pp:1-16 [Journal]
  133. Luis A. Castillo, Juan Fernández-Olivares, Antonio González
    Mixing expressiveness and efficiency in a manufacturing planner. [Citation Graph (0, 0)][DBLP]
    J. Exp. Theor. Artif. Intell., 2001, v:13, n:2, pp:141-162 [Journal]
  134. Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
    Dynamic Register Renaming Through Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  135. F. Jesús Sánchez, Antonio González
    Clustered Modulo Scheduling in a VLIW Architecture with Distributed Cache . [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
  136. F. Jesús Sánchez, Antonio González
    Software Data Prefetching for Software Pipelined Loops. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:58, n:2, pp:236-259 [Journal]
  137. Jaume Abella, Ramon Canal, Antonio González
    Power- and Complexity-Aware Issue Queue Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:5, pp:50-58 [Journal]
  138. F. Jesús Sánchez, Antonio González
    Analyzing Data Locality in Numeric Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2000, v:20, n:4, pp:58-66 [Journal]
  139. Luis Díaz de Cerio, Miguel Valero-García, Antonio González
    A Method for Exploiting Communication/Computation Overlap in Hypercubes. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1998, v:24, n:2, pp:221-245 [Journal]
  140. Dolors Royo, Miguel Valero-García, Antonio González
    Implementing the one-sided Jacobi method on a 2D/3D mesh multicomputer. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2001, v:27, n:9, pp:1253-1271 [Journal]
  141. Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, Llorenc Cruz, Fernando Latorre, Antonio González, Mateo Valero
    Errata on "Measuring Experimental Error in Microprocessor Simulation". [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2002, v:30, n:1, pp:2-4 [Journal]
  142. Alex Pajuelo, Antonio González, Mateo Valero
    Speculative execution for hiding memory latency. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:49-56 [Journal]
  143. Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle
    IATAC: a smart predictor to turn-off L2 cache lines. [Citation Graph (0, 0)][DBLP]
    TACO, 2005, v:2, n:1, pp:55-77 [Journal]
  144. Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli
    Removing communications in clustered microarchitectures through instruction replication. [Citation Graph (0, 0)][DBLP]
    TACO, 2004, v:1, n:2, pp:127-151 [Journal]
  145. Juan L. Aragón, José M. González, Antonio González
    Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:3, pp:281-291 [Journal]
  146. Enric Gibert, F. Jesús Sánchez, Antonio González
    Distributed Data Cache Designs for Clustered VLIW Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:10, pp:1227-1241 [Journal]
  147. José González, Antonio González
    Control-Flow Speculation through Value Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:12, pp:1362-1376 [Journal]
  148. Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt
    Lifetime-Sensitive Modulo Scheduling in a Production Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:3, pp:234-249 [Journal]
  149. Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González
    Modulo Scheduling with Reduced Register Pressure. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:6, pp:625-638 [Journal]
  150. Pedro Marcuello, Antonio González, Jordi Tubella
    Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:2, pp:114-125 [Journal]
  151. Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero
    Late Allocation and Early Release of Physical Registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:10, pp:1244-1259 [Journal]
  152. Joan-Manuel Parcerisa, Antonio González
    Improving Latency Tolerance of Multithreading through Decoupling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:10, pp:1084-1094 [Journal]
  153. Nigel P. Topham, Antonio González
    Randomized Cache Placement for Eliminating Conflicts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:2, pp:185-192 [Journal]
  154. Dolors Royo, Antonio González, Miguel Valero-García
    Low Communication Overhead Jacobi Algorithms for Eigenvalues Computation on Hypercubes. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 1999, v:14, n:2, pp:171-193 [Journal]
  155. Xavier Vera, Jaume Abella, Josep Llosa, Antonio González
    An accurate cost model for guiding data locality transformations. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2005, v:27, n:5, pp:946-987 [Journal]
  156. Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González
    A fast and accurate framework to analyze and optimize cache memory behavior. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2004, v:26, n:2, pp:263-300 [Journal]
  157. Luis Díaz de Cerio, Miguel Valero-García, Antonio González
    Hypercube Algorithms on Mesh Connected Multicomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2002, v:13, n:12, pp:1247-1260 [Journal]
  158. Antonio González, Miguel Valero-García, Luis Díaz de Cerio
    Executing Algorithms with Hypercube Topology on Torus Multicomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:8, pp:803-814 [Journal]
  159. Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González
    On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:2, pp:130-144 [Journal]
  160. A. González, N. Marín, O. Pons, M. A. Vila
    Qualification of Fuzzy Statements Under Fuzzy Certainty. [Citation Graph (0, 0)][DBLP]
    IFSA, 2007, pp:162-170 [Conf]
  161. Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González
    Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:15-22 [Conf]
  162. Osman S. Unsal, James Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin
    Impact of Parameter Variations on Circuits and Microarchitecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:6, pp:30-39 [Journal]
  163. Ronny Ronen, Antonio González
    Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:8-11 [Journal]
  164. Pedro Chaparro, José González, Grigorios Magklis, Qiong Cai, Antonio González
    Understanding the Thermal Implications of Multi-Core Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1055-1065 [Journal]

  165. Early Register Release for Out-of-Order Processors with RegisterWindows. [Citation Graph (, )][DBLP]


  166. FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery. [Citation Graph (, )][DBLP]


  167. Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading. [Citation Graph (, )][DBLP]


  168. Meeting points: using thread criticality to adapt multicore hardware to parallel regions. [Citation Graph (, )][DBLP]


  169. Key Microarchitectural Innovations for Future Microprocessors. [Citation Graph (, )][DBLP]


  170. Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. [Citation Graph (, )][DBLP]


  171. Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs. [Citation Graph (, )][DBLP]


  172. A Knowledge Engineering Methodology for Rapid Prototyping of Planning Applications. [Citation Graph (, )][DBLP]


  173. P-slice based efficient speculative multithreading. [Citation Graph (, )][DBLP]


  174. Improving Branch Prediction and Predicated Execution in Out-of-Order Processors. [Citation Graph (, )][DBLP]


  175. Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs. [Citation Graph (, )][DBLP]


  176. The auction: optimizing banks usage in Non-Uniform Cache Architectures. [Citation Graph (, )][DBLP]


  177. SCIS: Combining Instance Selection Methods to Increase Their Effectiveness over a Wide Range of Domains. [Citation Graph (, )][DBLP]


  178. On-Line Failure Detection and Confinement in Caches. [Citation Graph (, )][DBLP]


  179. Online error detection and correction of erratic bits in register files. [Citation Graph (, )][DBLP]


  180. A software-hardware hybrid steering mechanism for clustered microarchitectures. [Citation Graph (, )][DBLP]


  181. Efficient resources assignment schemes for clustered multithreaded processors. [Citation Graph (, )][DBLP]


  182. Boosting single-thread performance in multi-core systems through fine-grain multi-threading. [Citation Graph (, )][DBLP]


  183. End-to-end register data-flow continuous self-test. [Citation Graph (, )][DBLP]


  184. Thread fusion. [Citation Graph (, )][DBLP]


  185. MODEST: a model for energy estimation under spatio-temporal variability. [Citation Graph (, )][DBLP]


  186. Penelope: The NBTI-Aware Processor. [Citation Graph (, )][DBLP]


  187. Low Vccmin fault-tolerant cache with highly predictable performance. [Citation Graph (, )][DBLP]


  188. Current issues and future directions in evolutionary fuzzy systems research. [Citation Graph (, )][DBLP]


  189. An inductive approach for learning fuzzy relation rules. [Citation Graph (, )][DBLP]


  190. Tuning fuzzy logic controllers for energy efficiency consumption in buildings. [Citation Graph (, )][DBLP]


  191. Exploiting Narrow Values for Soft Error Tolerance. [Citation Graph (, )][DBLP]


Search in 0.015secs, Finished in 0.844secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002