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Ben H. H. Juurlink: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ben H. H. Juurlink, Stamatis Vassiliadis, Dmitri Tcheressiz, Harry A. G. Wijshoff
    Implementation and Evaluation of the Complex Streamed Instruction Set. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2001, pp:73-82 [Conf]
  2. Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis
    Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    ASAP, 2005, pp:393-398 [Conf]
  3. Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis
    Limitations of special-purpose instructions for similarity measurements in media SIMD extensions. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:293-303 [Conf]
  4. Pepijn J. de Langen, Ben H. H. Juurlink
    Reducing traffic generated by conflict misses in caches. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:235-239 [Conf]
  5. Peter Groen, Panu Hämäläinen, Ben H. H. Juurlink, Timo Hämäläinen
    Accelerating the secure remote password protocol using reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:471-480 [Conf]
  6. Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis
    Improving the memory behavior of vertical filtering in the discrete wavelet transform. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:253-260 [Conf]
  7. Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis
    Matrix register file and extended subwords: two techniques for embedded media processors. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:171-179 [Conf]
  8. Ben H. H. Juurlink
    Approximating the optimal replacement algorithm. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:313-319 [Conf]
  9. Ben H. H. Juurlink, Pepijn J. de Langen
    Dynamic techniques to reduce memory traffic in embedded systems. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2004, pp:192-201 [Conf]
  10. Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha
    Scene Management Models and Overlap Tests for Tile-Based Rendering. [Citation Graph (0, 0)][DBLP]
    DSD, 2004, pp:424-431 [Conf]
  11. Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff
    Implementation of a Streaming Execution Unit. [Citation Graph (0, 0)][DBLP]
    DSD, 2002, pp:156-165 [Conf]
  12. Ben H. H. Juurlink
    Unified Dual Data Caches. [Citation Graph (0, 0)][DBLP]
    DSD, 2003, pp:33-40 [Conf]
  13. Sorin Cotofana, Ben H. H. Juurlink, Stamatis Vassiliadis
    Counter Based Superscalar Instruction Issuing. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1307-1315 [Conf]
  14. Stamatis Vassiliadis, Ben H. H. Juurlink, Edwin Hakkennes
    Complex Streamed Instructions: Introduction and Initial Evaluatio. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1400-0 [Conf]
  15. Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff
    Performance Scalability of Multimedia Instruction Set Extensions. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2002, pp:849-860 [Conf]
  16. Ben H. H. Juurlink, P. S. Rao, Jop F. Sibeyn
    Worm-Hole Gossiping on Meshes. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:361-369 [Conf]
  17. Ben H. H. Juurlink, Harry A. G. Wijshoff
    The E-BSP Model: Incorporating General Locality and Unbalanced Communication into the BSP Model. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:339-347 [Conf]
  18. Dmitri Tcheressiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff
    Performance of the Complex Streamed Instruction Set on Image Processing Kernels. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2001, pp:678-686 [Conf]
  19. Olaf Bonorden, Ben H. H. Juurlink, Ingo von Otte, Ingo Rieping
    The Paderborn University BSP (PUB) Library - Design, Implementation and Performance. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:99-104 [Conf]
  20. Ben H. H. Juurlink
    Experimental Validation of Parallel Computation Models on the Intel Paragon. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:492-497 [Conf]
  21. Pyrrhos Stathis, Dmitry Cheresiz, Stamatis Vassiliadis, Ben H. H. Juurlink
    Sparse Matrix Transpose Unit. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  22. Pepijn J. de Langen, Ben H. H. Juurlink
    Leakage-aware multiprocessor scheduling for low power. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  23. Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis
    Accelerating Color Space Conversion Using Extended Subwords and the Matrix Register File. [Citation Graph (0, 0)][DBLP]
    ISM, 2006, pp:37-46 [Conf]
  24. Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha
    GraalBench: a 3D graphics benchmark suite for mobile phones. [Citation Graph (0, 0)][DBLP]
    LCTES, 2004, pp:1-9 [Conf]
  25. Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff
    Architectural Support for 3D Graphics in the Complex Streamed Instruction Set. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2002, pp:531-536 [Conf]
  26. Stephan Suijkerbuijk, Ben H. H. Juurlink
    Implementing Hardware Multithreading in a VLIW Architecture. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2005, pp:674-679 [Conf]
  27. Ben H. H. Juurlink, Harry A. G. Wijshoff
    Experiences with a Model for Parallel Computation. [Citation Graph (0, 0)][DBLP]
    PODC, 1993, pp:87-96 [Conf]
  28. Ben H. H. Juurlink, Asadollah Shahbahrami, Stamatis Vassiliadis
    Avoiding data conversions in embedded media processors. [Citation Graph (0, 0)][DBLP]
    SAC, 2005, pp:901-902 [Conf]
  29. Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha
    Memory Bandwidth Requirements of Tile-Based Rendering. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:323-332 [Conf]
  30. Ben H. H. Juurlink, Petr Kolman, Friedhelm Meyer auf der Heide, Ingo Rieping
    Optimal broadcast on parallel locality models. [Citation Graph (0, 0)][DBLP]
    SIROCCO, 2000, pp:221-225 [Conf]
  31. Micah Adler, Wolfgang Dittrich, Ben H. H. Juurlink, Miroslaw Kutylowski, Ingo Rieping
    Communication-Optimal Parallel Minimum Spanning Tree Algorithms (Extended Abstract). [Citation Graph (0, 0)][DBLP]
    SPAA, 1998, pp:27-36 [Conf]
  32. Harry A. G. Wijshoff, Ben H. H. Juurlink
    A Quantitative Comparison of Parallel Computation Models. [Citation Graph (0, 0)][DBLP]
    SPAA, 1996, pp:13-24 [Conf]
  33. Ben H. H. Juurlink, Harry A. G. Wijshoff
    The Parallel Hierarchical Memory Model. [Citation Graph (0, 0)][DBLP]
    SWAT, 1994, pp:240-251 [Conf]
  34. Asadollah Shahbahrami, Ben H. H. Juurlink, Demid Borodin, Stamatis Vassiliadis
    Avoiding Conversion and Rearrangement Overhead in SIMD Architectures. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2006, v:34, n:3, pp:237-260 [Journal]
  35. Ben H. H. Juurlink, Harry A. G. Wijshoff
    Communication Primitives for BSP Computers. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1996, v:58, n:6, pp:303-310 [Journal]
  36. Ben H. H. Juurlink, Petr Kolman, Friedhelm Meyer auf der Heide, Ingo Rieping
    Optimal broadcast on parallel locality models. [Citation Graph (0, 0)][DBLP]
    J. Discrete Algorithms, 2003, v:1, n:2, pp:151-166 [Journal]
  37. Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff
    Implementation of a streaming execution unit. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:599-617 [Journal]
  38. Olaf Bonorden, Ben H. H. Juurlink, Ingo von Otte, Ingo Rieping
    The Paderborn University BSP (PUB) library. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2003, v:29, n:2, pp:187-207 [Journal]
  39. Ben H. H. Juurlink, Harry A. G. Wijshoff
    A Quantitative Comparison of Parallel Computation Models. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Comput. Syst., 1998, v:16, n:3, pp:271-318 [Journal]
  40. Ben H. H. Juurlink, Jop F. Sibeyn, P. S. Rao
    Gossiping on Meshes and Tori. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:6, pp:513-525 [Journal]
  41. Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff
    The CSI multimedia architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:1-13 [Journal]
  42. Demid Borodin, Ben H. H. Juurlink, Stamatis Vassiliadis
    Instruction-Level Fault Tolerance Configurability. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:110-117 [Conf]
  43. Pepijn J. de Langen, Ben H. H. Juurlink
    Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:75-85 [Conf]

  44. Performance Improvement of Multimedia Kernels by Alleviating Overhead Instructions on SIMD Devices. [Citation Graph (, )][DBLP]


  45. SIMD Vectorization of Histogram Functions. [Citation Graph (, )][DBLP]


  46. Memory copies in multi-level memory systems. [Citation Graph (, )][DBLP]


  47. Scalar Processing Overhead on SIMD-Only Architectures. [Citation Graph (, )][DBLP]


  48. Specialization of the Cell SPE for Media Applications. [Citation Graph (, )][DBLP]


  49. Protective redundancy overhead reduction using instruction vulnerability factor. [Citation Graph (, )][DBLP]


  50. Limiting the number of dirty cache lines. [Citation Graph (, )][DBLP]


  51. Instruction precomputation with memoization for fault detection. [Citation Graph (, )][DBLP]


  52. A Low-Cost Cache Coherence Verification Method for Snooping Systems. [Citation Graph (, )][DBLP]


  53. Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. [Citation Graph (, )][DBLP]


  54. Instruction Precomputation for Fault Detection. [Citation Graph (, )][DBLP]


  55. SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform. [Citation Graph (, )][DBLP]


  56. (When) Will CMPs Hit the Power Wall?. [Citation Graph (, )][DBLP]


  57. Introduction. [Citation Graph (, )][DBLP]


  58. Extending the Cell SPE with Energy Efficient Branch Prediction. [Citation Graph (, )][DBLP]


  59. Parallel H.264 Decoding on an Embedded Multicore Processor. [Citation Graph (, )][DBLP]


  60. Evaluation of parallel H.264 decoding strategies for the Cell Broadband Engine. [Citation Graph (, )][DBLP]


  61. Analysis of video filtering on the cell processor. [Citation Graph (, )][DBLP]


  62. Optimization of Content-Based Image Retrieval Functions. [Citation Graph (, )][DBLP]


  63. GRAAL: A Framework for Low-Power 3D Graphics Accelerators. [Citation Graph (, )][DBLP]


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