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Author:
Prithviraj Banerjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. A. L. Narasimha Reddy, Prithviraj Banerjee
    An Evaluation of Multiple-Disk I/O Systems. [Citation Graph (6, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:12, pp:1680-1690 [Journal]
  2. Krishna P. Belkhale, Prithviraj Banerjee
    An Approximate Algorithm for the Partitionable Independent Task Scheduling Problem. [Citation Graph (2, 0)][DBLP]
    ICPP (1), 1990, pp:72-75 [Conf]
  3. Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee
    A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers. [Citation Graph (1, 0)][DBLP]
    ICPP, 1994, pp:116-125 [Conf]
  4. Prithviraj Banerjee, Jacob A. Abraham
    Fault-Secure Algorithms for Multiple-Processor Systems. [Citation Graph (1, 0)][DBLP]
    ISCA, 1984, pp:279-287 [Conf]
  5. A. L. Narasimha Reddy, Prithviraj Banerjee
    Design, Analysis, and Simulation of I/O Architectures for Hypercube. [Citation Graph (1, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1990, v:1, n:2, pp:140-151 [Journal]
  6. Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee
    A Matrix-Based Approach to the Global Locality Optimization Problem. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1998, pp:306-313 [Conf]
  7. Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee
    On Reducing False Sharing while Improving Locality on Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 1999, pp:203-211 [Conf]
  8. Pramod G. Joisha, Prithviraj Banerjee
    Correctly detecting intrinsic type errors in typeless languages such as MATLAB. [Citation Graph (0, 0)][DBLP]
    APL, 2001, pp:7-21 [Conf]
  9. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
    Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:645-648 [Conf]
  10. Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee
    An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:28-33 [Conf]
  11. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
    Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. [Citation Graph (0, 0)][DBLP]
    CASES, 2000, pp:85-93 [Conf]
  12. Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee
    PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:188-197 [Conf]
  13. Pramod G. Joisha, Prithviraj Banerjee
    The MAGICA Type Inference Engine for MATLAB. [Citation Graph (0, 0)][DBLP]
    CC, 2003, pp:121-125 [Conf]
  14. Daniel J. Palermo, Eugene W. Hodges IV, Prithviraj Banerjee
    Compiler Optimization of Dynamic Data Distributions for Distributed-Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    Compiler Optimizations for Scalable Parallel Systems Languages, 2001, pp:445-484 [Conf]
  15. Randall J. Brouwer, Prithviraj Banerjee
    PHIGURE: A Parallel Hierarchical Global Router. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:650-653 [Conf]
  16. Vivek Chickermane, Elizabeth M. Rudnick, Prithviraj Banerjee, Janak H. Patel
    Non-Scan Design-for-Testability Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:236-241 [Conf]
  17. Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
    An Efficient Assertion Checker for Combinational Properties. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:734-739 [Conf]
  18. Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
    An Implicit Algorithm for Finding Steady States and its Application to FSM Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:611-614 [Conf]
  19. M. Jones, Prithviraj Banerjee
    Performance of a Parallel Algorithm for Standard Cell Placement on the Intel Hypercube. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:807-813 [Conf]
  20. Victor Kim, Prithviraj Banerjee
    Parallel Algorithms for Power Estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:672-677 [Conf]
  21. SungHo Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel
    APT: An Area-Performance-Testability Driven Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:141-146 [Conf]
  22. Ralph-Michael Kling, Prithviraj Banerjee
    ESP: A New Standard Cell Placement Package Using Simulated Evolution. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:60-66 [Conf]
  23. Ralph-Michael Kling, Prithviraj Banerjee
    Optimization by Simulated Evolution with Applications to Standard Cell Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:20-25 [Conf]
  24. Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee
    Automatic translation of software binaries onto FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:389-394 [Conf]
  25. Steven Parkes, Prithviraj Banerjee, Janak H. Patel
    ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:717-721 [Conf]
  26. Srinivas Patil, Prithviraj Banerjee
    A Parallel Branch and Bound Algorithm for Test Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:339-343 [Conf]
  27. Srinivas Patil, Prithviraj Banerjee, Janak H. Patel
    Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:155-159 [Conf]
  28. Sanghamitra Roy, Prithviraj Banerjee
    An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:484-487 [Conf]
  29. Sumit Roy, Krishna P. Belkhale, Prithviraj Banerjee
    An Approxmimate Algorithm for Delay-Constraint Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:367-372 [Conf]
  30. Jeff S. Sargent, Prithviraj Banerjee
    A Parallel Row-based Algorithm for Standard Cell Placement with Integrated Error Control. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:590-593 [Conf]
  31. Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee
    Leakage power optimization with dual-Vth library in high-level synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:202-207 [Conf]
  32. Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh
    Potential-NRG: Placement with Incomplete Data. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:279-282 [Conf]
  33. Nikolaos D. Liveris, Prithviraj Banerjee
    Power Aware Interface Synthesis for Bus-Based SoC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:864-869 [Conf]
  34. Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou
    Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:618-623 [Conf]
  35. Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee
    Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:722-728 [Conf]
  36. Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee
    Accurate Area and Delay Estimators for FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:862-869 [Conf]
  37. Sumit Roy, Harm Arts, Prithviraj Banerjee
    PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:967-968 [Conf]
  38. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary
    A System-Level Synthesis Algorithm with Guaranteed Solution Quality. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:417-0 [Conf]
  39. Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu
    A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. I, 1996, pp:828-831 [Conf]
  40. Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Nagaraj Shenoy, Prithviraj Banerjee
    Enhancing Spatial Locality via Data Layout Optimizations. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:422-434 [Conf]
  41. Prithviraj Banerjee, Debabrata Bagchi, Malay Haldar, Anshuman Nayak, Victor Kim, R. Uribe
    Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:263-264 [Conf]
  42. Prithviraj Banerjee, Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky
    A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:39-48 [Conf]
  43. Alex K. Jones, Prithviraj Banerjee
    An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:284-285 [Conf]
  44. David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee
    Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:37-46 [Conf]
  45. Prithviraj Banerjee, Vikram Saxena, J. R. Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, R. Anderson
    Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:237- [Conf]
  46. Alex K. Jones, Prithviraj Banerjee
    An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:244- [Conf]
  47. Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee
    High level area, delay and power estimation for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:249- [Conf]
  48. Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee
    An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:256- [Conf]
  49. Zhi Alex Ye, Nagaraj Shenoy, Prithviraj Banerjee
    A C compiler for a processor with a reconfigurable functional unit. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:95-100 [Conf]
  50. Amitabh Mishra, Prithviraj Banerjee
    An Algorithm Based Error Detection Scheme for the Multigrid Algorithm. [Citation Graph (0, 0)][DBLP]
    FTCS, 1999, pp:12-19 [Conf]
  51. Michael Peercy, Prithviraj Banerjee
    Design and Analysis of Software Reconfiguration Strategies for Hypercube Multicomputers under Multiple Faults. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:448-455 [Conf]
  52. Michael Peercy, Prithviraj Banerjee
    Software Schemes of Reconfiguration and Recovery in Distributed Memory Multicomputers Using the Actor Model. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:479-488 [Conf]
  53. A. L. Narasimha Reddy, Prithviraj Banerjee
    Gracefully Degradable Disk Arrays. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:401-409 [Conf]
  54. Amber Roy-Chowdhury, Prithviraj Banerjee
    Tolerance Determination for Algorithm-Based Checks Using Simplified Error Analysis Techniques. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:290-298 [Conf]
  55. Amber Roy-Chowdhury, Prithviraj Banerjee
    Algorithm-Based Fault Location and Recovery for Matrix Computations. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:38-47 [Conf]
  56. Amber Roy-Chowdhury, Prithviraj Banerjee
    Compiler-Assisted Generation of Error-Detecting Parallel Programs. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:360-369 [Conf]
  57. Jim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran
    An Incremental Floorplanner. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:248-251 [Conf]
  58. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
    Parallel algorithms for FPGA placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:86-94 [Conf]
  59. Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee
    Macro-models for high level area and power estimation on FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:162-165 [Conf]
  60. Yanhong Yuan, Prithviraj Banerjee
    ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:64-67 [Conf]
  61. David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee
    Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:397-400 [Conf]
  62. John G. Holm, Steven Parkes, Prithviraj Banerjee
    Performance Evaluation of a C++ Library Based Multithreaded System. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1997, pp:282-291 [Conf]
  63. Yanhong Yuan, Prithviraj Banerjee
    A Parallel 3-D Capacitance Extraction Program. [Citation Graph (0, 0)][DBLP]
    HiPC, 1999, pp:202-206 [Conf]
  64. David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham
    SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:66-69 [Conf]
  65. Krishna P. Belkhale, Prithviraj Banerjee
    A Parallel Algorithm for Hierarchical Circuit Extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:236-239 [Conf]
  66. Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee
    ProperSYN: a portable parallel algorithm for logic synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:412-416 [Conf]
  67. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee
    A System for Synthesizing Optimized FPGA Hardware from MATLAB. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:314-319 [Conf]
  68. Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
    Efficient equivalence checking of multi-phase designs using retiming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:557-562 [Conf]
  69. Balkrishna Ramkumar, Prithviraj Banerjee
    Portable parallel test generation for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:220-223 [Conf]
  70. Sumit Roy, Harm Arts, Prithviraj Banerjee
    PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:601-606 [Conf]
  71. John A. Chandy, Prithviraj Banerjee
    A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:621-627 [Conf]
  72. Pradeep Prabhakaran, Prithviraj Banerjee
    Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:66-71 [Conf]
  73. Steven Parkes, Prithviraj Banerjee, Janak H. Patel
    A parallel algorithm for fault simulation based on PROOFS . [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:616-0 [Conf]
  74. Balkrishna Ramkumar, Prithviraj Banerjee
    ProperCAd: A Portable Object-Oriented Parallel Environment for VLSI CAD. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:544-548 [Conf]
  75. Yanhong Yuan, Prithviraj Banerjee
    Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:133-0 [Conf]
  76. A. L. Narasimha Reddy, Prithviraj Banerjee
    A Fault Secure Dictionary Machine. [Citation Graph (0, 6)][DBLP]
    ICDE, 1987, pp:104-110 [Conf]
  77. Kaushik De, Prithviraj Banerjee
    Parallel Logic Synthesis Using Partitioning. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1994, pp:135-142 [Conf]
  78. Vijay Balasubramanian, Prithviraj Banerjee
    RECBAR : A Reconfigurable Massively Parallel Processing Architecture. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:390-393 [Conf]
  79. Vijay Balasubramanian, Prithviraj Banerjee
    CRAFT: Compiler-Assisted Algorithm-Based Fault Tolerance in Distributed Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:501-504 [Conf]
  80. Prithviraj Banerjee, Abhijeet Dugar
    A Fault-Tolerant Interconnection Network Supporting the Fetch-And-Add Primitive. [Citation Graph (0, 0)][DBLP]
    ICPP, 1986, pp:327-334 [Conf]
  81. Krishna P. Belkhale, Prithviraj Banerjee
    Geometric Connected Component Labeling on Distributed Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1990, pp:291-294 [Conf]
  82. John A. Chandy, Prithviraj Banerjee
    Reliability Evalutaion of Disk Array Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:263-267 [Conf]
  83. Malay Haldar, Anshuman Nayak, Abhay Kanhere, Pramod G. Joisha, Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee
    Match Virtual Machine: An Adaptive Runtime System to Execute MATLAB in Parallel. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:145-152 [Conf]
  84. Gagan Hasteer, Prithviraj Banerjee
    A Parallel Algorithm for State Assignment of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    ICPP, Vol. 2, 1996, pp:37-45 [Conf]
  85. Jiun-Ming Hsu, Prithviraj Banerjee
    Hardware Support for Message Routing in a Distributed Memory Multicomputer. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:508-515 [Conf]
  86. Jiun-Ming Hsu, Prithviraj Banerjee
    Performance Evaluation of Hardware Support for Message Passing in Distributed Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1991, pp:604-607 [Conf]
  87. John G. Holm, Prithviraj Banerjee
    Low Cost Concurrent Error Detection in a VLIW Architecture Using Replicated Instructions. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1992, pp:192-195 [Conf]
  88. Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee
    A Framework for Interprocedural Locality Optimization Using Both Loop and Data Layout Transformations. [Citation Graph (0, 0)][DBLP]
    ICPP, 1999, pp:95-102 [Conf]
  89. Mahmut T. Kandemir, Nagaraj Shenoy, Prithviraj Banerjee, J. Ramanujam, Alok N. Choudhary
    Minimizing Data and Synchronization Costs in One-Way Communication. [Citation Graph (0, 0)][DBLP]
    ICPP, 1998, pp:180-188 [Conf]
  90. Victor Kim, Prithviraj Banerjee, Kaushik De
    Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:421-0 [Conf]
  91. Dilip Krishnaswamy, Prithviraj Banerjee
    Exploiting task and data parallelism in parallel Hough and Radon transforms. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:441-0 [Conf]
  92. Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee
    Load Balancing and Workload Minimization Of Overlapping Parallel Tasks. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:272-279 [Conf]
  93. Robert B. Mueller-Thuns, David McFarland, Prithviraj Banerjee
    Algorithm-Based Fault Tolerance for Adaptive Least Squares Lattice Filtering on a Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1989, pp:177-180 [Conf]
  94. Daniel J. Palermo, Ernesto Su, John A. Chandy, Prithviraj Banerjee
    Communication Optimizations Used in the PARADIGM Compiler for Distributed Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    ICPP, 1994, pp:1-10 [Conf]
  95. Daniel J. Palermo, Ernesto Su, Eugene W. Hodges IV, Prithviraj Banerjee
    Compiler Support for Privatization on Distributed-Memory Machines. [Citation Graph (0, 0)][DBLP]
    ICPP, Vol. 3, 1996, pp:17-24 [Conf]
  96. Shankar Ramaswamy, Prithviraj Banerjee
    Processor Allocation and Scheduling of Macro Dataflow Graphs on Distributed Memory Multicomputers by the PARADIGM Compiler. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:134-138 [Conf]
  97. A. L. Narasimha Reddy, Prithviraj Banerjee
    I/O Embedding in Hypercubes. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:331-338 [Conf]
  98. A. L. Narasimha Reddy, Prithviraj Banerjee
    Performance Evaluation of Multiple-Disk I/O Systems. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1989, pp:315-318 [Conf]
  99. A. L. Narasimha Reddy, Prithviraj Banerjee, D. K. Chen
    Compiler Support for Parallel I/O Operations. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1991, pp:290-291 [Conf]
  100. Amber Roy-Chowdhury, Prithviraj Banerjee
    A Fault-Tolerant Parallel Algorithm for Iterative Solution of the Laplace Equation. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:133-140 [Conf]
  101. Ernesto Su, Daniel J. Palermo, Prithviraj Banerjee
    Automating Parallelization of Regular Computations for Distributed-Memory. [Citation Graph (0, 0)][DBLP]
    ICPP, 1993, pp:30-38 [Conf]
  102. Zhaoyun Xing, Prithviraj Banerjee
    A Parallel Algorithm for Timing-driven Global Routing for Standard Cells. [Citation Graph (0, 0)][DBLP]
    ICPP, 1998, pp:54-61 [Conf]
  103. Dhruva R. Chakrabarti, Prithviraj Banerjee
    Global optimization techniques for automatic parallelization of hybrid applications. [Citation Graph (0, 0)][DBLP]
    ICS, 2001, pp:166-180 [Conf]
  104. Dhruva R. Chakrabarti, Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee
    An Efficient Uniform Run-time Scheme for Mixed Regular-irregular Applications. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:61-68 [Conf]
  105. Manish Gupta, Prithviraj Banerjee
    A methodology for high-level synthesis of communication on multicomputers. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:357-367 [Conf]
  106. Manish Gupta, Prithviraj Banerjee
    PARADIGM: A Compiler for Automatic Data Distribution on Multicomputers. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:87-96 [Conf]
  107. Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Eduard Ayguadé
    An integer linear programming approach for optimizing cache locality. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:500-509 [Conf]
  108. Mahmut T. Kandemir, Alok N. Choudhary, Nagaraj Shenoy, Prithviraj Banerjee, J. Ramanujam
    A Hyperplane Based Approach for Optimizing Spatial Locality in Loop Nests. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:69-76 [Conf]
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    Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:172-179 [Conf]
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    Parallel Compiled Event Driven VHDL Simulation. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:297-304 [Conf]
  111. Antonio Lain, Prithviraj Banerjee
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    International Conference on Supercomputing, 1994, pp:236-245 [Conf]
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    Compiler Support for Hybrid Irregular Accesses on Multicomputers. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1996, pp:1-9 [Conf]
  113. A. L. Narasimha Reddy, Prithviraj Banerjee
    I/O issues for hypercubes. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:72-81 [Conf]
  114. Ernesto Su, Antonio Lain, Shankar Ramaswamy, Daniel J. Palermo, Eugene W. Hodges IV, Prithviraj Banerjee
    Advanced Compilation Techniques in the PARADIGM Compiler for Distributed-memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1995, pp:424-433 [Conf]
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    Processor Tagged Descriptors: A Data Structure for Compiling for Distributed-Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:123-132 [Conf]
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    A Scheduling Algorithm for Parallelizable Dependent Tasks. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:500-506 [Conf]
  117. Dhruva R. Chakrabarti, Prithviraj Banerjee
    A Novel Compilation Framework for Supporting Semi-Regular Distributions in Hybrid Applications. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:597-602 [Conf]
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    Evaluation of Compiler and Runtime Library Approaches for Supporting Parallel Regular Applications. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:74-79 [Conf]
  119. Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, Prithviraj Banerjee
    Parallel algorithms for logic synthesis using the MIS approach. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:579-585 [Conf]
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    Compile-Time Estimation of Communication Costs on Multicomputers. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:470-475 [Conf]
  121. Pramod G. Joisha, Prithviraj Banerjee
    PARADIGM (version 2.0): A New HPF Compilation System. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:609-615 [Conf]
  122. Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Nagaraj Shenoy
    A Generalized Framework for Global Communication Optimization. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:69-73 [Conf]
  123. Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee
    A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1999, pp:738-743 [Conf]
  124. SungHo Kim, Prithviraj Banerjee, Balkrishna Ramkumar, Steven Parkes, John A. Chandy
    ProperPLACE: A Portable Parallel Algorithm for Standard Cell Placement. [Citation Graph (0, 0)][DBLP]
    IPPS, 1994, pp:932-941 [Conf]
  125. Antonio Lain, Prithviraj Banerjee
    Exploiting spatial regularity in irregular iterative applications. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:820-826 [Conf]
  126. Shankar Ramaswamy, Eugene W. Hodges IV, Prithviraj Banerjee
    Compiling MATLAB Programs to ScaLAPACK: Exploiting Task and Data Parallelism. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:613-619 [Conf]
  127. Balkrishna Ramkumar, Prithviraj Banerjee
    A Portable Parallel Algorithm for VLSI Circuit Extraction. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:434-438 [Conf]
  128. Sumit Roy, Prithviraj Banerjee
    A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:665-671 [Conf]
  129. Zhaoyun Xing, John A. Chandy, Prithviraj Banerjee
    Parallel Global Routing Algorithms for Standard Cells. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:527-0 [Conf]
  130. Yanhong Yuan, Prithviraj Banerjee
    A Parallel Implementation of a Fast Multipole Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputer. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:323-330 [Conf]
  131. John A. Chandy, Steven Parkes, Prithviraj Banerjee
    Distributed Object Oriented Data Structures and Algorithms for VLSI CAD. [Citation Graph (0, 0)][DBLP]
    IRREGULAR, 1996, pp:147-158 [Conf]
  132. Jiun-Ming Hsu, Prithviraj Banerjee
    Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:260-269 [Conf]
  133. A. L. Narasimha Reddy, Prithviraj Banerjee
    A Study of I/O Behavior of Perfect Benchmarks on a Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1990, pp:312-321 [Conf]
  134. Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee
    CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:225-235 [Conf]
  135. Zhaoyun Xing, Prithviraj Banerjee
    A parallel algorithm for zero skew clock tree routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:118-123 [Conf]
  136. Yanhong Yuan, Prithviraj Banerjee
    Incremental capacitance extraction and its application to iterative timing-driven detailed routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:42-47 [Conf]
  137. Rajarshi Mukherjee, Alex K. Jones, Prithviraj Banerjee
    Handling Data Streams while Compiling C Programs onto Hardware. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:271-272 [Conf]
  138. Kaushik De, Prithviraj Banerjee
    Logic Partitioning and Resynthesis for Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:906-915 [Conf]
  139. Prithviraj Banerjee, Jacob A. Abraham
    Generating Tests for Physical Failures in MOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:554-559 [Conf]
  140. SungHo Kim, Prithviraj Banerjee, Srinivas Patil
    A Layout Driven Design for Testability Technique for MOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:157-165 [Conf]
  141. Srinivas Patil, Prithviraj Banerjee
    Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:718-726 [Conf]
  142. Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi
    A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs. [Citation Graph (0, 0)][DBLP]
    IWDC, 2002, pp:246-256 [Conf]
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    Accurate Data and Context Management in Message-Passing Programs. [Citation Graph (0, 0)][DBLP]
    LCPC, 1999, pp:117-132 [Conf]
  144. Pramod G. Joisha, Prithviraj Banerjee
    Exploiting Ownership Sets in HPF. [Citation Graph (0, 0)][DBLP]
    LCPC, 2000, pp:259-273 [Conf]
  145. Pramod G. Joisha, Nagaraj Shenoy, Prithviraj Banerjee
    Computing Array Shapes in MATLAB. [Citation Graph (0, 0)][DBLP]
    LCPC, 2001, pp:395-410 [Conf]
  146. Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary, Prithviraj Banerjee
    A Loop Transformation Algorithm Based on Explicit Data Layout Representation for Optimizing Locality. [Citation Graph (0, 0)][DBLP]
    LCPC, 1998, pp:34-50 [Conf]
  147. Daniel J. Palermo, Prithviraj Banerjee
    Automatic Selection of Dynamic Data Partitioning Schemes for Distributed-Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    LCPC, 1995, pp:392-406 [Conf]
  148. Daniel J. Palermo, Eugene W. Hodges IV, Prithviraj Banerjee
    Interprocedural Array Redistribution Data-Flow Analysis. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:435-449 [Conf]
  149. Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee
    Improving Locality Using Loop and Data Transformations in an Integrated Framework. [Citation Graph (0, 0)][DBLP]
    MICRO, 1998, pp:285-297 [Conf]
  150. Venkatram Krishnaswamy, Prithviraj Banerjee
    Actor Based Parallel VHDL Simulation Using Time Warp. [Citation Graph (0, 0)][DBLP]
    Workshop on Parallel and Distributed Simulation, 1996, pp:135-142 [Conf]
  151. Dilip Krishnaswamy, Prithviraj Banerjee, Elizabeth M. Rudnick, Janak H. Patel
    Asynchronous Parallel Algorithms for Test Set Partitioned Fault Simulation. [Citation Graph (0, 0)][DBLP]
    Workshop on Parallel and Distributed Simulation, 1997, pp:30-37 [Conf]
  152. Pramod G. Joisha, Prithviraj Banerjee
    Static array storage optimization in MATLAB. [Citation Graph (0, 0)][DBLP]
    PLDI, 2003, pp:258-268 [Conf]
  153. Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee
    Improving Locality Using a Graph-Based Technique for Detecting Memory Layouts of Arrays. [Citation Graph (0, 0)][DBLP]
    PPSC, 1999, pp:- [Conf]
  154. Vijay Balasubramanian, Prithviraj Banerjee
    A Fixed Size Array Processor for Computing the Fast Fourier Transform. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1987, pp:36-43 [Conf]
  155. Vijay Balasubramanian, Prithviraj Banerjee
    Algorithm-based Error Detection for Signal Processing Applications on a Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP]
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  156. Prithviraj Banerjee, Jacob A. Abraham
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  157. Jiun-Ming Hsu, Prithviraj Banerjee
    A message passing coprocessor for distributed memory multicomputers. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:720-729 [Conf]
  158. Steven Parkes, John A. Chandy, Prithviraj Banerjee
    A library-based approach to portable, parallel, object-oriented programming: interface, implementation, and application. [Citation Graph (0, 0)][DBLP]
    SC, 1994, pp:69-78 [Conf]
  159. John A. Chandy, Prithviraj Banerjee
    Parallel simulated annealing strategies for VLSI cell placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:37-42 [Conf]
  160. Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee, Nagaraj Shenoy
    Fpga Hardware Synthesis From Matlab. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:299-304 [Conf]
  161. Gagan Hasteer, Prithviraj Banerjee
    Simulated Annealing Based Parallel State Assignment of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:69-75 [Conf]
  162. Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee
    Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:475-481 [Conf]
  163. Chieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga
    A Shared Memory Parallel Algorithm for Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:317-322 [Conf]
  164. Pradeep Prabhakaran, Prithviraj Banerjee
    Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:428-434 [Conf]
  165. Pradeep Prabhakaran, Prithviraj Banerjee, Jim E. Crenshaw, Majid Sarrafzadeh
    Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization. [Citation Graph (0, 0)][DBLP]
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  166. Sumit Roy, Prithviraj Banerjee, Majid Sarrafzadeh
    Partitioning sequential circuits for low power. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:212-217 [Conf]
  167. U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary, Mahmut T. Kandemir
    Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators. [Citation Graph (0, 0)][DBLP]
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  168. Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee
    Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:267-273 [Conf]
  169. Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee
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  170. Prithviraj Banerjee, John A. Chandy, Manish Gupta, Eugene W. Hodges IV, John G. Holm, Antonio Lain, Daniel J. Palermo, Shankar Ramaswamy, Ernesto Su
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  175. Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee
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  176. Ky MacPherson, Prithviraj Banerjee
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  177. Daniel J. Palermo, Eugene W. Hodges IV, Prithviraj Banerjee
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  178. A. L. Narasimha Reddy, John A. Chandy, Prithviraj Banerjee
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    J. Parallel Distrib. Comput., 1993, v:17, n:1-2, pp:28-40 [Journal]
  179. Shankar Ramaswamy, Barbara Simons, Prithviraj Banerjee
    Optimizations for Efficient Array Redistribution on Distributed Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
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  180. Yanhong Yuan, Prithviraj Banerjee
    A Parallel Implementation of a Fast Multipole-Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
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  181. Shankar Ramaswamy, Prithviraj Banerjee
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  186. Prithviraj Banerjee, Michael Peercy
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    IEEE Trans. Computers, 1994, v:43, n:7, pp:841-848 [Journal]
  187. Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham
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  188. Krishna P. Belkhale, Prithviraj Banerjee
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    IEEE Trans. Computers, 1992, v:41, n:1, pp:83-96 [Journal]
  189. Krishna P. Belkhale, Prithviraj Banerjee
    Parallel Algorithms for Geometric Connected Component Labeling on a Hypercube Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:6, pp:699-709 [Journal]
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    IEEE Trans. Computers, 1996, v:45, n:2, pp:238-243 [Journal]
  191. Gagan Hasteer, Prithviraj Banerjee
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  192. Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary, Prithviraj Banerjee
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  193. Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee
    Automatic Parallelization of Compiled Event Driven VHDL Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:4, pp:380-394 [Journal]
  194. Amitabh Mishra, Prithviraj Banerjee
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    IEEE Trans. Computers, 2003, v:52, n:9, pp:1089-1099 [Journal]
  195. V. S. S. Nair, Jacob A. Abraham, Prithviraj Banerjee
    Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:499-503 [Journal]
  196. Pradeep Prabhakaran, Prithviraj Banerjee
    Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:7, pp:762-768 [Journal]
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  198. Amber Roy-Chowdhury, Prithviraj Banerjee
    Algorithm-Based Fault Location and Recovery for Matrix Computations on Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:11, pp:1239-1247 [Journal]
  199. Amber Roy-Chowdhury, Nikolas Bellas, Prithviraj Banerjee
    Algorithm-Based Error Detection Schemes for Iterative Solution of Partial Differential Equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:394-407 [Journal]
  200. Douglas B. West, Prithviraj Banerjee
    On the Construction of Communication Networks Satisfying Bounded Fan-In of Service Ports. [Citation Graph (0, 0)][DBLP]
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  201. Prithviraj Banerjee, Jacob A. Abraham
    A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:312-321 [Journal]
  202. Krishna P. Belkhale, Prithviraj Banerjee
    Parallel algorithms for VLSI circuit extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:604-618 [Journal]
  203. Krishna P. Belkhale, Randall J. Brouwer, Prithviraj Banerjee
    Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:557-567 [Journal]
  204. John A. Chandy, SungHo Kim, Balkrishna Ramkumar, Steven Parkes, Prithviraj Banerjee
    An evaluation of parallel simulated annealing strategies with application to standard cell placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:4, pp:398-410 [Journal]
  205. Kaushik De, Balkrishna Ramkumar, Prithviraj Banerjee
    A portable parallel algorithm for logic synthesis using transduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:566-580 [Journal]
  206. Ralph-Michael Kling, Prithviraj Banerjee
    ESp: Placement by simulated evolution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:245-256 [Journal]
  207. Ralph-Michael Kling, Prithviraj Banerjee
    Empirical and theoretical studies of the simulated evolution method applied to standard cell placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:10, pp:1303-1315 [Journal]
  208. Srinivas Patil, Prithviraj Banerjee
    A parallel branch and bound algorithm for test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:3, pp:313-322 [Journal]
  209. Srinivas Patil, Prithviraj Banerjee
    Performance trade-offs in a parallel test generation/fault simulation environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1542-1558 [Journal]
  210. Balkrishna Ramkumar, Prithviraj Banerjee
    ProperCAD: A portable object-oriented parallel environment for VLSI CAD. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:7, pp:829-842 [Journal]
  211. Balkrishna Ramkumar, Prithviraj Banerjee
    ProperTEST: a portable parallel test generator for sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:555-569 [Journal]
  212. Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
    Efficient equivalence checking of multi-phase designs using phase abstraction and retiming. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:600-625 [Journal]
  213. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee
    An algorithm for synthesis of large time-constrained heterogeneous adaptive systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:2, pp:207-225 [Journal]
  214. Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Nagaraj Shenoy
    A global communication optimization technique based on data-flow analysis and linear algebra. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1999, v:21, n:6, pp:1251-1297 [Journal]
  215. Pramod G. Joisha, Prithviraj Banerjee
    An algebraic array shape inference system for MATLAB. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 2006, v:28, n:5, pp:848-907 [Journal]
  216. Prithviraj Banerjee, Mark Howard Jones, Jeff S. Sargent
    Parallel Simulated Annealing Algorithms for Cell Placement on Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1990, v:1, n:1, pp:91-106 [Journal]
  217. Manish Gupta, Prithviraj Banerjee
    Demonstration of Automatic Data Partitioning Techniques for Parallelizing Compilers on Multicomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:2, pp:179-193 [Journal]
  218. Jiun-Ming Hsu, Prithviraj Banerjee
    Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:4, pp:451-464 [Journal]
  219. Pramod G. Joisha, Prithviraj Banerjee
    The Efficient Computation of Ownership Sets in HPF. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:8, pp:769-788 [Journal]
  220. Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam, Eduard Ayguadé
    Static and Dynamic Locality Optimizations Using Integer Linear Programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2001, v:12, n:9, pp:922-941 [Journal]
  221. Mahmut T. Kandemir, Alok N. Choudhary, Prithviraj Banerjee, J. Ramanujam, Nagaraj Shenoy
    Minimizing Data and Synchronization Costs in One-Way Communication. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:12, pp:1232-1251 [Journal]
  222. Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee
    Reducing False Sharing and Improving Spatial Locality in a Unified Compilation Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:4, pp:337-354 [Journal]
  223. Mahmut T. Kandemir, Alok N. Choudhary, Nagaraj Shenoy, Prithviraj Banerjee, J. Ramanujam
    A Linear Algebra Framework for Automatic Determination of Optimal Data Layouts. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:2, pp:115-135 [Journal]
  224. Antonio Lain, Dhruva R. Chakrabarti, Prithviraj Banerjee
    Compiler and Run-Time Support for Exploiting Regularity within Irregular Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:2, pp:119-135 [Journal]
  225. Shankar Ramaswamy, Sachin S. Sapatnekar, Prithviraj Banerjee
    A Framework for Exploiting Task and Data Parallelism on Distributed Memory Multicomputers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:11, pp:1098-1116 [Journal]
  226. Vijay Balasubramanian, Prithviraj Banerjee
    Tradeoffs in the Design of Efficient Algorithm-Based Error Detection Schemes for Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1990, v:16, n:2, pp:183-196 [Journal]
  227. Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, R. Anderson, J. R. Uribe
    Overview of a compiler for synthesizing MATLAB programs onto FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:312-324 [Journal]
  228. Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee
    An Overview of a Compiler for Mapping Software Binaries to Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1177-1190 [Journal]
  229. Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel
    Sequential circuit testability enhancement using a nonscan approach. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:333-338 [Journal]
  230. Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee
    High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:259-272 [Journal]

  231. Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. [Citation Graph (, )][DBLP]


  232. Retiming for Synchronous Data Flow Graphs. [Citation Graph (, )][DBLP]


  233. A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications. [Citation Graph (, )][DBLP]


  234. State space abstraction for parameterized self-stabilizing embedded systems. [Citation Graph (, )][DBLP]


  235. Streaming implementation of a sequential decompression algorithm on an FPGA. [Citation Graph (, )][DBLP]


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