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Paolo Ienne: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marc Epalza, Paolo Ienne, Daniel Mlynek
    Adding Limited Reconfigurability to Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    IEEE PACT, 2004, pp:53-62 [Conf]
  2. Marc Epalza, Paolo Ienne, Daniel Mlynek
    Dynamic Reallocation of Functional Units in Superscalar Processors. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:185-198 [Conf]
  3. Paolo Ienne
    Horizontal Microcode Compaction for Programmable Systolic Accelerators. [Citation Graph (0, 0)][DBLP]
    ASAP, 1995, pp:85-0 [Conf]
  4. Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli
    Automatic Instruction Set Extension and Utilization for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ASAP, 2003, pp:108-0 [Conf]
  5. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    ASAP, 2004, pp:339-351 [Conf]
  6. Frederic Worm, Patrick Thiran, Paolo Ienne
    A Unified Coding Framework for Delay-Insensitivity. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2005, pp:201-211 [Conf]
  7. Laura Pozzi, Paolo Ienne
    Exploiting pipelining to relax register-file port constraints of instruction-set extensions. [Citation Graph (0, 0)][DBLP]
    CASES, 2005, pp:2-10 [Conf]
  8. Miljan Vuletic, Christophe Dubach, Laura Pozzi, Paolo Ienne
    Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:243-248 [Conf]
  9. Kubilay Atasu, Laura Pozzi, Paolo Ienne
    Automatic application-specific instruction-set extensions under microarchitectural constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:256-261 [Conf]
  10. Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil Dutt
    Introduction of local memory elements in instruction set extensions. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:729-734 [Conf]
  11. Paolo Ienne, Alexander Grießing
    Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:396-401 [Conf]
  12. Ajay K. Verma, Paolo Ienne
    Towards the automatic exploration of arithmetic-circuit architectures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:445-450 [Conf]
  13. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Virtual memory window for application-specific reconfigurable coprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:948-953 [Conf]
  14. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1246-1251 [Conf]
  15. Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
    Automatic identification of application-specific functional units with architecturally visible storage. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:212-217 [Conf]
  16. Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma
    Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:218-223 [Conf]
  17. Laura Pozzi, Miljan Vuletic, Paolo Ienne
    Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1138- [Conf]
  18. Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne
    Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:748- [Conf]
  19. Paolo Ienne, Ajay K. Verma
    Arithmetic Transformations to Maximise the Use of Compressor Trees. [Citation Graph (0, 0)][DBLP]
    DELTA, 2004, pp:219-224 [Conf]
  20. Soner Yaldiz, Alper Demir, Serdar Tasiran, Paolo Ienne, Yusuf Leblebici
    Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. [Citation Graph (0, 0)][DBLP]
    ESTImedia, 2005, pp:135-140 [Conf]
  21. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:24-33 [Conf]
  22. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:596-605 [Conf]
  23. Ajay K. Verma, Paolo Ienne
    Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:791-798 [Conf]
  24. Frederic Worm, Paolo Ienne, Patrick Thiran
    Soft self-synchronising codes for self-calibrating communication. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:440-447 [Conf]
  25. Frederic Worm, Patrick Thiran, Paolo Ienne
    Designing Robust Checkers in the Presence of Massive Timing Errors. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:281-286 [Conf]
  26. Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne
    Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1782-1785 [Conf]
  27. Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
    Self-calibrating networks-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2361-2364 [Conf]
  28. Francesco Mondada, Edoardo Franzi, Paolo Ienne
    Mobile Robot Miniaturisation: A Tool for Investigation in Control Algorithms. [Citation Graph (0, 0)][DBLP]
    ISER, 1993, pp:501-513 [Conf]
  29. Frederic Worm, Patrick Thiran, Paolo Ienne
    Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:861-866 [Conf]
  30. M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha
    A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:2-7 [Conf]
  31. Paolo Ienne, Patrick Thiran, Giovanni De Micheli, Frederic Worm
    An Adaptive Low-Power Transmission Scheme for On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:92-100 [Conf]
  32. Paolo Ienne
    Digital Connectionist Hardware: Current Problems and Future Challenges. [Citation Graph (0, 0)][DBLP]
    IWANN, 1997, pp:688-713 [Conf]
  33. Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne
    Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:17-32 [Conf]
  34. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi
    Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:651-656 [Conf]
  35. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Seamless Hardware-Software Integration in Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:2, pp:102-113 [Journal]
  36. Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
    On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:6, pp:524-535 [Journal]
  37. Kubilay Atasu, Laura Pozzi, Paolo Ienne
    Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2003, v:31, n:6, pp:411-428 [Journal]
  38. Paolo Ienne, Marc A. Viredaz
    Bit-Serial Multipliers and Squarers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:12, pp:1445-1450 [Journal]
  39. Laura Pozzi, Kubilay Atasu, Paolo Ienne
    Exact and approximate algorithms for the extension of embedded processor instruction sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1209-1229 [Journal]
  40. Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli
    A robust self-calibrating transmission scheme for on-chip networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:126-139 [Journal]
  41. Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:7, pp:754-762 [Journal]
  42. Miljan Vuletic, Laura Pozzi, Paolo Ienne
    Virtual memory window for application-specific reconfigurable coprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:910-915 [Journal]
  43. Ajay K. Verma, Philip Brisk, Paolo Ienne
    Rethinking custom ISE identification: a new processor-agnostic method. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:125-134 [Conf]
  44. Philip Brisk, Ajay K. Verma, Paolo Ienne
    An optimistic and conservative register assignment heuristic for chordal graphs. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:209-217 [Conf]
  45. Ajay K. Verma, Philip Brisk, Paolo Ienne
    Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:404-409 [Conf]
  46. Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar
    Enhancing FPGA Performance for Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:334-337 [Conf]
  47. Ajay K. Verma, Paolo Ienne
    Automatic synthesis of compressor trees: reevaluating large counters. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:443-448 [Conf]
  48. Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
    A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:209-214 [Conf]
  49. Derin Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici
    A Predictable Communication Scheme for Embedded Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:152-157 [Conf]
  50. Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, Paolo Ienne
    ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  51. Challenges in Automatic Optimization of Arithmetic Circuits. [Citation Graph (, )][DBLP]


  52. Hybrid LZA: a near optimal implementation of the leading zero anticipator. [Citation Graph (, )][DBLP]


  53. Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. [Citation Graph (, )][DBLP]


  54. Efficient synthesis of compressor trees on FPGAs. [Citation Graph (, )][DBLP]


  55. Fast, quasi-optimal, and pipelined instruction-set extensions. [Citation Graph (, )][DBLP]


  56. Design space exploration for field programmable compressor trees. [Citation Graph (, )][DBLP]


  57. A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. [Citation Graph (, )][DBLP]


  58. Speculative DMA for architecturally visible storage in instruction set extensions. [Citation Graph (, )][DBLP]


  59. Way Stealing: cache-assisted automatic instruction set extensions. [Citation Graph (, )][DBLP]


  60. Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. [Citation Graph (, )][DBLP]


  61. Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. [Citation Graph (, )][DBLP]


  62. Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. [Citation Graph (, )][DBLP]


  63. Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?. [Citation Graph (, )][DBLP]


  64. FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. [Citation Graph (, )][DBLP]


  65. Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. [Citation Graph (, )][DBLP]


  66. A novel FPGA logic block for improved arithmetic performance. [Citation Graph (, )][DBLP]


  67. 3D configuration caching for 2D FPGAs. [Citation Graph (, )][DBLP]


  68. Exploiting fast carry-chains of FPGAs for designing compressor trees. [Citation Graph (, )][DBLP]


  69. Using 3D integration technology to realize multi-context FPGAs. [Citation Graph (, )][DBLP]


  70. MPSoC Design Using Application-Specific Architecturally Visible Communication. [Citation Graph (, )][DBLP]


  71. Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. [Citation Graph (, )][DBLP]


  72. Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. [Citation Graph (, )][DBLP]


  73. Memory organization and data layout for instruction set extensions with architecturally visible storage. [Citation Graph (, )][DBLP]


  74. Iterative layering: Optimizing arithmetic circuits by structuring the information flow. [Citation Graph (, )][DBLP]


  75. Error Protected Data Bus Inversion Using Standard DRAM Components. [Citation Graph (, )][DBLP]


  76. Introducing control-flow inclusion to support pipelining in custom instruction set extensions. [Citation Graph (, )][DBLP]


  77. Arithmetic optimization for custom instruction set synthesis. [Citation Graph (, )][DBLP]


  78. Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. [Citation Graph (, )][DBLP]


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